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MAGNACHIP SEMICONDUCTOR LTD. 8-BIT SINGLE-CHIP MICROCONTROLLERS
MC80F0208/16/24 MC80C0208/16/24
User's Manual (Ver. 0.2) Preliminary
REVISION HISTORY
VERSION 0.2 (MAR. 2005) This book
Version 0.2 Published by MCU Application Team 2005 MagnaChip semiconductor Inc. All right reserved.
Additional information of this manual may be served by MagnaChip semiconductor offices in Korea or Distributors and Representatives. MagnaChip semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, MagnaChip semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
MC80F0208/16/24
1. OVERVIEW .................................................................................................................................................... 1 Description .................................................................................................................................................... 1 Features ........................................................................................................................................................ 1 Ordering Information ............................................................... ................................................................ 2 Development Tools ....................................................................................................................................... 3 2. BLOCK DIAGRAM ........................................................................................................................................ 4 3. PIN ASSIGNMENT ........................................................................................................................................ 5 4. PACKAGE DIAGRAM ................................................................................................................................... 6 5. PIN FUNCTION .............................................................................................................................................. 7 Pin Description .............................................................................................................................................. 8 6. PORT STRUCTURES .................................................................................................................................. 10 7. ELECTRICAL CHARACTERISTICS ........................................................................................................... 13 Absolute Maximum Ratings ........................................................................................................................ 13 Recommended Operating Conditions ......................................................................................................... 13 A/D Converter Characteristics .................................................................................................................... 13 DC Electrical Characteristics ...................................................................................................................... 14 AC Characteristics ...................................................................................................................................... 15 Serial Interface Timing Characteristics ....................................................................................................... 16 Typical Characteristic Curves ..................................................................................................................... 17 8. MEMORY ORGANIZATION ........................................................................................................................ 19 Registers ..................................................................................................................................................... 19 Program Memory ........................................................................................................................................ 21 Data Memory .............................................................................................................................................. 25 Addressing Mode ........................................................................................................................................ 31 9. I/O PORTS ................................................................................................................................................... 35 10. CLOCK GENERATOR .............................................................................................................................. 39 11. BASIC INTERVAL TIMER ......................................................................................................................... 40 12. WATCHDOG TIMER ................................................................................................................................. 42 13. WATCH TIMER .......................................................................................................................................... 45 14. TIMER/EVENT COUNTER ........................................................................................................................ 46 8-bit Timer / Counter Mode ......................................................................................................................... 50 16-bit Timer / Counter Mode ....................................................................................................................... 56 8-bit Compare Output (16-bit) ..................................................................................................................... 57 8-bit Capture Mode ..................................................................................................................................... 58 16-bit Capture Mode ................................................................................................................................... 62 PWM Mode ................................................................................................................................................. 65 15. ANALOG TO DIGITAL CONVERTER ....................................................................................................... 68 16. SERIAL INPUT/OUTPUT (SIO) ................................................................................................................. 71 Transmission/Receiving Timing .................................................................................................................. 72 The method of Serial I/O ............................................................................................................................. 74 The Method to Test Correct Transmission .................................................................................................. 74 17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) ................................................... 75 UART Serial Interface Functions ................................................................................................................ 75
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Serial Interface Configuration ..................................................................................................................... 77 Communication operation ........................................................................................................................... 80 Relationship between main clock and baud rate ........................................................................................ 82 18. BUZZER FUNCTION ................................................................................................................................. 83 19. INTERRUPTS ............................................................................................................................................ 85 Interrupt Sequence ..................................................................................................................................... 87 BRK Interrupt .............................................................................................................................................. 89 Shared Interrupt Vector ............................................................................................................................... 89 Multi Interrupt .............................................................................................................................................. 90 External Interrupt ........................................................................................................................................ 91 20. OPERATION MODE .................................................................................................................................. 93 Operation Mode Switching .......................................................................................................................... 93 21. POWER SAVING OPERATION ................................................................................................................ 94 Sleep Mode ................................................................................................................................................. 94 Stop Mode ................................................................................................................................................... 95 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode ..................................................................... 98 Minimizing Current Consumption .............................................................................................................. 100 22. OSCILLATOR CIRCUIT .......................................................................................................................... 102 23. RESET ..................................................................................................................................................... 103 24. POWER FAIL PROCESSOR ................................................................................................................... 104 25. FLASH PROGRAMMING ........................................................................................................................ 106 Device Configuration Area ........................................................................................................................ 106 26. Emulator EVA. Board Setting .............................................................................................................. 107 27. IN-SYSTEM PROGRAMMING (ISP) ....................................................................................................... 110 Getting Started / Installation ...................................................................................................................... 110 Basic ISP S/W Information ........................................................................................................................ 110 Hardware Conditions to Enter the ISP Mode ............................................................................................ 111 Reference ISP Circuit diagram ................................................................................................................. 113 A. INSTRUCTION ............................................................................................................................................... i Terminology List ..............................................................................................................................................i Instruction Map ..............................................................................................................................................ii Instruction Set ............................................................................................................................................... iii B. MASK ORDER SHEET ................................................................................................................................ ix
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MC80F0208/16/24
MC80F0208/16/24 MC80C0208/16/24
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 10-BIT A/D CONVERTER AND UART
1. OVERVIEW
1.1 Description
The MC80F0208/16/24 is advanced CMOS 8-bit microcontroller with 8K/16K/24K bytes of FLASH(ROM). This is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following standard features : 8K/16K/24K bytes of FLASH, 1K bytes of RAM, 8/16-bit timer/counter, watchdog timer, watch timer, 10-bit A/D converter, 8-bit Serial Input/Output, UART, buzzer driving port, 10-bit PWM output and on-chip oscillator and clock circuitry. It also has 8 high current I/O pins with typical 20mA. In addition, the MC80F0208/16/24 supports power saving modes to reduce power consumption. Device Name FLASH MC80F0208Q MC80F0208K MC80F0216Q MC80F0216K MC80F0224Q MC80F0224K MASK ROM MC80C0208Q MC80C0208K MC80C0216Q MC80C0216K MC80C0224Q MC80C0224K FLASH(ROM) Size 8KByte
RAM 1024 Byte 1024 Byte 1024 Byte
ADC
PWM
I/O PORT
Package 44MQFP 42SDIP 44MQFP 42SDIP 44MQFP 42SDIP
8 channel
1 channel
36 port
16KByte
8 channel
1 channel
36 port
24KByte
8 channel
1 channel
36 port
1.2 Features
* 8K/16K/24K Bytes On-chip ROM * FLASH Mermory - Endurance : 100 cycles - Data Retention : 10 years * 1024 Bytes On-chip Data RAM (Included stack memory) * Minimum Instruction Execution Time - 333ns at 12MHz (NOP instruction) * 36 I/O Ports * One 8-bit Basic Interval Timer * Four 8-bit and one 16-bit Timer/Event counter (or three 16-bit Timer/Event counter) * One Watchdog timer * One Watch timer * One 10-bit PWM * 8 channel 10-bit A/D converter * Three 8-bit Serial Communication Interface - One Serial I/O and two UART * One Buzzer Driving port - 488Hz ~ 250kHz@4MHz * Four External Interrupt input ports * Fifteen Interrupt sources - Basic Interval Timer(1) - External input(4) - Timer/Event counter(5) - ADC(1) - Serial Interface(1), UART(2) - WDT and Watch Timer(1) * Built in Noise Immunity Circuit - Noise filter - 3-level Power fail detector [3.0V, 2.7V, 2.4V] * Power Down Mode - Stop, Sleep mode * Operating Voltage Range - 2.7V ~ 5.5V (@ 8MHz) - 4.5V ~ 5.5V (@ 12MHz)
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* Operating Frequency Range - 0.4 ~ 12MHz * 44MQFP, 42SDIP type * Operating Temperature : -40C ~ 85C
* Oscillator Type - Crystal, Ceramic resonator, External clock
1.3 Ordering Information
ROM Type Device name MC80C0208Q MC80C0208K Mask version MC80C0216Q MC80C0216K MC80C0224Q MC80C0224K MC80F0208Q MC80F0208K FLASH version MC80F0216Q MC80F0216K MC80F0224Q MC80F0224K ROM Size 8K bytes 8K bytes 16K bytes 16K bytes 24K bytes 24K bytes 8K bytes FLASH 8K bytes FLASH 16K bytes FLASH 16K bytes FLASH 24K bytes FLASH 24K bytes FLASH RAM size 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes Package 44MQFP 42SDIP 44MQFP 42SDIP 44MQFP 42SDIP 44MQFP 42SDIP 44MQFP 42SDIP 44MQFP 42SDIP
Table 1-1 Ordering Information of MC80F0208/16/24 & MC80C0208/16/24
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MC80F0208/16/24
1.4 Development Tools
The MC80F0208/16/24 is supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.TM and OTP programmers. There are two different type of programmers such as single type and gang type. For mode detail, Macro assembler operates under the MS-Windows 95 and upversioned Windows OS. Please contact sales part of MagnaChip semiconductor. - MS-Windows based assembler - MS-Windows based Debugger - MC800 C compiler - CHOICE-Dr. - CHOICE-Dr. EVA80C0x B/D - CHOICE - SIGMA I/II(Single writer) - PGM Plus I/II/III(Single writer) - Standalone GANG4 I/II(Gang writer) Choice-Dr. (Emulator)
Software Hardware (Emulator) FLASH Writer
PGMplus III ( Single Writer )
Standalone Gang4 II ( Gang Writer )
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2. BLOCK DIAGRAM
ADC Power Supply AVDD
Power Supply VDD VSS
R00~R07
R0
PSW
ALU
A
X
Y
Stack Pointer
Data Memory (1024 bytes)
PC
Interrupt Controller 8-bit Basic Interval Timer Watch/ Watchdog Timer 8-bit Timer/ Counter 10-bit PWM 8-bit serial Interface SIO/UART0 10-bit ADC 8-bit serial Interface UART1
Program Memory Data Table
System controller System Clock Controller Timing Generator Clock Generator
Instruction Decoder
Driver Buzzer
R1
R5
R4
R6
R3
R10/INT0 R11/INT1 R12/INT2 R13/BUZO R15/EC0
R40 R50/INT3 R41 R51/EC1 R54/PWM3O/T3O R42/SCK R43/SI R44/SO R45/ACLK0 R46/RxD0 R47/TxD0
R60/AN0 R61/AN1 R62/AN2 R63/AN3 R64/AN4 R65/AN5 R66/AN6 R67/AN7
RESET
R30 R31/ACLK1 R32/RxD1 R33/TxD1
4
XOUT
XIN
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MC80F0208/16/24
3. PIN ASSIGNMENT
42SDIP (Top View)
VDD AN4 / R64 AN5 / R65 AN6 / R66 AN7 / R67 R00 R01 R02 R03 R04 R05 R06 R07 INT0 / R10 INT1 / R11 INT2 / R12 BUZO / R13 EC0 / R15 RESET XIN XOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
R63 / AN3 R62 / AN2 R61 / AN1 R60 / AN0 R54 / PWM3O / T3O AVDD R51 / EC1 R50 / INT3 R47 / TxD0 R46 / RxD0 R45 / ACLK0 R44 / SO R43 / SI R42 / SCK R41 R40 R33 / TxD1 R32 / RxD1 R31 / ACLK1 R30 VSS
MC80F0208K/16K/24K
T3O / PWM3O / R54 AN0 / R60 AN1 / R61 AN2 / R62 AN3 / R63 VDD AN4 / R64 AN5 / R65 AN6 / R66 AN7 / R67 NC
34 35 36 37 38 39 40 41 42 43 44
33 32 31 30 29 28 27 26 25 24 23
AVDD R51 / EC1 R50 / INT3 R47 / TxD0 R46 / RxD0 R45 / ACLK0 R44 / SO R43 / SI R42 / SCK R41 R40
44MQFP (Top View)
22 21 20 19 18 MC80F0208Q/16Q/24Q 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11
NC R33 / TxD1 R32 / RxD1 R31 / ACLK1 R30 VSS XOUT XIN RESET R15 / EC0 R13 / BUZO
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R00 R01 R02 R03 R04 R05 R06 R07 INT0 / R10 INT1 / R11 INT2 / R12
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4. PACKAGE DIAGRAM
42SDIP
UNIT: INCH
1.470 1.450 0.190 max. min. 0.015 0.600 BSC 0.550 0.530
0.140 0.120
0.020 0.016
0.045 0.035
0.070 BSC
0-15
0.012 0.008
44MQFP UNIT: MM
13.45 12.95 10.10 9.90
13.45 12.95 10.10 9.90
2.10 1.95
0-7 SEE DETAIL "A" 0.25 0.10 1.03 0.73 1.60 BSC 0.45 0.30 0.80 BSC DETAIL "A"
2.35 max.
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MC80F0208/16/24
5. PIN FUNCTION
VDD: Supply voltage. VSS: Circuit ground. AVDD: Supply voltage to the ladder resistor of ADC circuit. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins with 1 or 0 written to the R0 Port Direction Register R0IO can be used as outputs or inputs. The internal pull-up resistor can be connected by using the pull-up selection register 0 (PU0). R10~R13, R15: R1 is an 5-bit CMOS bidirectional I/O port. R1 pins with 1 or 0 written to the R1 Port Direction Register R1IO can be used as outputs or inputs. The internal pull-up resistor can be connected by using the pull-up selection register 1 (PU1). In addition, R1 serves the functions of the various following special features such as INT0 (External interrupt 0), INT1 (External interrupt 1), INT2 (External interrupt 2), BUZO (Buzzer driver output), EC0 (Event counter input 0). R30~R33: R3 is an 4-bit CMOS bidirectional I/O port. R3 pins with 1 or 0 written to the R3 Port Direction Register R3IO can be used as outputs or inputs. R3 operates as the high current output port with typical 20mA at low level output. In addition, R3 serves the functions of the following special features such as ACLK1 (UART1 Asynchronous serial clock input), RxD1 (UART1 data input), TxD1 (UART1 data output). R40~R47: R4 is an 8-bit CMOS bidirectional I/O port. R4 pins with 1 or 0 written to the R4 Port Direction Register R4IO can be used as outputs or inputs. The internal pull-up resistor can be connected by using the pull-up selection register 4 (PU4). In addition, R4 serves the functions of the various following special features such as SCK (Serial clock), SI (Serial data input), SO (Serial data output), ACLK0 (UART1 Asynchronous serial clock input), RxD0 (UART0 data input), TxD0 (UART0 data output). R50, R51, R54: R5 is an 3-bit CMOS bidirectional I/O port. R5 pins with 1 or 0 written to the R5 Port Direction Register R5IO can be used as outputs or inputs. In addition, R5 serves the functions of the various following special features such as INT3 (External interrupt 3), EC1 (Event counter input 1), PWM3O (PWM output 3)/T3O(Timer3 Compare output). R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins with 1 or 0 written to the R6 Port Direction Register R6IO can be used as outputs or inputs. In addition, R6 serves the functions of the ADC analog input port AN[7:0].
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5.1 Pin Description
5.1.1 Normal Function Pin Description
PIN NAME In/Out Function Port0 8-bit I/O port. Can be set in input or output mode in 1-bit units. Internal pull-up resistor PU0 can be used via software. Port 1. 5-bit I/O port. Can be set in input or output mode in 1-bit units. Internal pull-up resistor PU1 can be used via software. Initial state Input Alternate Function INT0 INT1 Input INT2 BUZO EC0 I/O Port 3. 4-bit I/O port. Can be set in input or output mode in 1-bit units. Input ACLK1 RxD1 TxD1 Port 4. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Internal pull-up resistor PU4 can be used via software. SCK Input SI SO ACLK0 RxD0 TxD0 I/O Port 5. 3-bit I/O port. Can be set in input or output mode in 1-bit units. Port 6. 8-bit I/O port. Can be set in input or output mode in 1-bit units. System reset input. Crystal connection for main system clock oscillation. Analog power/reference voltage input to A/D converter. Set the same potential as VDD. Positive power supply. Ground potential. INT3 Input EC1 PWM3O/T3O Input Input Input Output AN0~AN7 I/O
R00~R07 R10 R11 R12 R13 R15 R30 R31 R32 R33 R40 R41 R42 R43 R44 R45 R46 R47 R50 R51 R54 R60~R67 RESET XIN XOUT AVDD VDD VSS
I/O
I/O
I/O I I O -
Table 5-1 Normal Function Pin Description
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MC80F0208/16/24
5.1.2 Alternate Function Pin Description
PIN NAME INT0 INT1 INT2 INT3 BUZO EC0 EC1 SCK SI SO ACLK0 RxD0 TxD0 ACLK1 RxD1 TxD1 PWM3O T3O AN0~AN7 O I I I/O I O I I O I I O O I Buzzer Output Timer0 Event Counter Input Timer2 Event Counter Input Serial clock input/output of serial interface. Serial data input of serial interface. Serial data output of serial interface. Asynchronous serial interface serial clock input. Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input2. Asynchronous serial interface serial data input2. Asynchronous serial interface serial data output2. Timer3 PWM Output Timer3 Compare Output Analog input Channel 0 ~ 7 for A/D converter. Input Input Input Input Input Input Input Input Input Input Input Input Output Input I Valid edges(rising, falling, or both rising and falling) can be specified. External Interrupt request Input. Input In/Out Function Initial state Shared Pin R10 R11 R12 R50 R13 R15 R51 R42 R43 R44 R45 R46 R47 R31 R32 R33 R54 R60~R67
Table 5-2 Alternate Function Pin Description
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6. PORT STRUCTURES
R00~R07, R40, R41 R13(BUZO), R47(TxD0)
VDD Pull-up Reg. VDD Data Reg. Pull-up Tr. VDD BUZO,TxD0 Data Reg. Direction Reg. VSS Data Bus VSS Pin Direction Reg. BUZO_EN,TxD0_EN MUX MUX Data Bus RD MUX Pull-up Reg.
VDD Pull-up Tr.
VDD
VDD
Pin
VSS
VSS
RD
R10(INT0)~ R12(INT2), R15(EC0), R43(SI), R45(ACLK0), R46(RxD0)
VDD Pull-up Reg. VDD Data Reg. Direction Reg. VSS Pull-up Tr. VDD
R30
VDD Data Reg.
VDD
Pin
Direction Reg. VSS VSS
Pin
VSS Data Bus MUX
Data Bus MUX
RD INT,EC,SI, RxD0, ACLK0 INT_EN, EC_EN SI_EN, ACLK0_EN, RxD0_EN Noise Filter
RD
10
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MC80F0208/16/24
R33(TxD1)
R44(SO, IOSWIN)
VDD Pull-up Reg. Pull-up Tr. VDD MUX Pin
TxD1 Data Reg. MUX
VDD
VDD
SO Data Reg. Pin Direction Reg.
VDD
Direction Reg. TxD1_EN VSS VSS
SO_EN Data Bus
VSS
VSS
MUX Data Bus IOSWIN_EN SI RD IOSWIN_EN
MUX RD Noise Filter
R42(SCK) R31(ACLK1), R32(RxD1), R50(INT3), R51(EC1)
VDD Pull-up Reg. SCK Data Reg. Direction Reg. SCKO_EN Data Bus MUX RD SCKI_EN SCK Noise Filter RD Noise Filter VSS VSS MUX VDD Pull-up Tr. Data Reg. VDD Direction Reg. Pin Pin VDD VDD
VSS Data Bus MUX
INT3, EC1 ACLK1, RxD1 INT3_EN, EC1_EN ACLK1_EN, RxD1_EN
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R54(PWM3O/T3O)
XIN, XOUT
VDD
PWM3O VDD Data Reg. MUX VDD XIN Pin VSS VSS VSS VDD Data Bus MUX MAIN CLOCK VSS STOP
Direction Reg. PWM3_EN
XOUT RD VSS
R60~R67(AN0~AN7)
VDD Data Reg. VDD
RESET
VDD
Mask only Direction Reg. VSS Data Bus MUX RD VSS Pin Pin Internal Reset
VSS
AN[7:0] ADC_EN & CH_SEL
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MC80F0208/16/24
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Parameter Supply Voltage Symbol VDD AVDD VI VO Normal Votagae Pin IOH IOH IOL IOL Total Power Dissipation Storage Temperature fXIN TSTG Rating -0.3 ~ +6.5 VDD - 0.3 ~ VDD +0.3 -0.3 ~ VDD +0.3 -0.3 ~ VDD +0.3 10 80 20 160 600 -65 ~ +150 Unit V V V V mA mA mA mA mW C Voltage on any pin with respect to Ground (VSS) Maximum output current sourced by (IOH per I/O Pin) Maximum current (IOH) Maximum current sunk by (IOL per I/O Pin) Maximum current (IOL) C Note -
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
Specifications Parameter Symbol Condition Min. Supply Voltage Operating Temperature VDD TOPR fXIN = 0.4 ~ 12MHz fXIN = 0.4 ~ 8MHz VDD = 4.5 ~ 5.5V 4.5 2.7 -40 Max. 5.5 5.5 85 V V C Unit
7.3 A/D Converter Characteristics
(Ta=-40~85C, VSS=0V, VDD= AVDD = 2.7~5.5V @fXIN=4MHz) Parameter Resolution Total Accuracy Intergral Linearity Error Differential Linearity Error Zero Offset Error Full Scale Error Conversion Time Symbol ILE DLE ZOE FSE tCON 10bit conversion fXIN = 4Mhz AVDD = VDD = 5.12V fXIN = 4Mhz Conditions Min. 13* Typ. 10 Max. 3 2 2 2 2 Unit BIT LSB LSB LSB LSB LSB S
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Parameter Analog Input Voltage Analog Power Supply Analog Ground Analog Input Current Analog Block Current
Symbol VAN AVDD VSS IADIN IADC
Conditions AVDD=VDD=5.12V AVDD=VDD=5.12V
Min. VSS VSS -
Typ. 200
Max. AVDD VDD VSS+0.3 10 300
Unit V V V A A
Note : 4MHz(fXIN) / 22 X 13Cycle = 13uS
7.4 DC Electrical Characteristics
(TA=-40~85C, VDD=5.0V10%, VSS=0V, fXIN=8MHz) Parameter Symbol VIH1 Input High Voltage VIH2 VIH3 VIL1 Input Low Voltage VIL2 VIL3 Output High Voltage VOH1 VOH2 VOL1 VOL2 IOL IIH IIL RPU RX IIL VT Pin/Condition INT0, INT1, INT2, INT3, EC0, EC1, SI, SCK, ACLK0, ACLK1, RxD0, RxD1, RESET R0, R1, R3, R4, R5, R6 XIN INT0, INT1, INT2, INT3, EC0, EC1, SI, SCK, ACLK0,ACLK1, RxD0, RxD1, RESET R0, R1, R3, R4, R5, R6 XIN R0, R1, R3, R4, R5, R6 (IOH=-0.7mA) XOUT (IOH=-50A) R0, R1, R3, R4, R5, R6 (IOL=1.6mA) XOUT (IOL=50A) R3 (VOL=1V) R0, R1, R3, R4, R5, R6 R0, R1, R3, R4, R5, R6 R0, R1, R4 XIN, XOUT VDD=4.5V INT0, INT1, INT2, INT3, EC0, EC1, SI, SCK, ACLK0, ACLK1, RxD0,RxD1 Min. 0.8VDD 0.7VDD 0.8VDD -0.3 -0.3 -0.3 VDD-0.4 VDD-0.5
-
Typ. 2.7 3.0 2.4
Max. VDD+0.3 VDD+0.3 VDD+0.3 0.2VDD 0.3VDD 0.2VDD 0.4 0.5 20 1 100 4.5 100 0.8 3.2 3.5 2.9
Unit V V V V V V V V V V mA A A k M S V V V V
Output Low Voltage High Current Input High Leakage Current Input Low Leakage Current Pull-up Resistor OSC Feedback Resistor Internal RC WDT Period (RCWDT) Hysteresis Power Fail Detect Voltage
-1 10 0.45 33 0.3 2.2
VPFD
2.5 1.9
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MC80F0208/16/24
Parameter
Symbol IDD1
Pin/Condition Active Mode, XIN=8MHz Sleep Mode, XIN=8MHz Stop Mode, Oscillator Stop, XIN=4MHz Stop Mode, Oscillator Stop, XIN=8MHz
Min. -
Typ. -
Max. 15 6 5 40
Unit mA mA A A
Power Supply Current
ISLEEP ISTOP IRCWDT
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7.5 AC Characteristics
(TA=-40~85C, VDD=5V10%, VSS=0V) Specifications Min. 0.4 35 2 8 2 Typ. Max. 12 20 20 20
Parameter Operating Frequency Oscillation Stabilizing Time (4MHz) External Clock Pulse Width External Clock Transition Time Interrupt Pulse Width RESET Input Width Event Counter Input Pulse Width Event Counter Transition Time
Symbol fXIN tST tCPW tRCP,tFCP tIW tRST tECW tREC,tFEC
Pins XIN XIN, XOUT XIN XIN INT0, INT1, INT2, INT3 RESET EC0, EC1 EC0, EC1
Unit MHz mS nS nS tSYS tSYS tSYS nS
tSYS = 1/fXIN
tCPW
tCPW VDD-0.5V
XIN
tRCP tIW tIW tFCP
0.5V
INT0~INT3
0.8VDD 0.2VDD
tRST
RESET
0.2VDD
tECW
tECW 0.8VDD 0.2VDD
EC0, EC1
tREC tFEC
Figure 7-1 Timing Chart
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7.6 Serial Interface Timing Characteristics
(TA=-40~+85C, VDD=5V10%, VSS=0V, fXIN=8MHz) Specifications Parameter Serial Input Clock Pulse Serial Input Clock Pulse Width Serial Input Clock Pulse Transition Time Serial Input Pulse Transition Time Serial Input Setup Time (External SCK) Serial Input Setup Time (Internal SCK) Serial Input Hold Time Serial Output Clock Cycle Time Serial Output Clock Pulse Width Serial Output Clock Pulse Transition Time Serial Output Delay Time Symbol tSCYC tSCKW tFSCK tRSCK tFSIN tRSIN tSUS tSUS tHS tSCYC tSCKW tFSCK tRSCK sOUT Pins Min. SCK SCK SCK SI SI SI SI SCK SCK SCK SO 2tSYS+200 tSYS+70 100 200 tSYS+70 4tSYS tSYS-30 30 100 Typ. 16tSYS Max. 30 30 nS nS nS nS nS nS nS nS nS nS nS Unit
tFSCK 0.8VDD 0.2VDD
tSCYC tRSCK tSCKW tSCKW
SCK
tSUS
tHS 0.8VDD 0.2VDD
SI
tDS tFSIN
tRSIN
SO
0.8VDD 0.2VDD
Figure 7-2 Serial I/O Timing Chart
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Preliminary
7.7 Typical Characteristic Curves
This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively where is standard deviation
IOH (mA) VDD=5.0V TA=25C -12 -9 -6 -3 0 0.5
IOH-VOH
R0,R1,R3~R6 pins
IOH (mA) VDD=3.0V TA=25C -12 -9 -6 -3 0
IOH-VOH
R0,R1,R3~R6 pins
1.0
1.5
2.0
2.5
VDD-VOH (V)
0.5
1.0
1.5
2.0 VDD-VOH (V)
IOL (mA) VDD=5.0V TA=25C 40 30 20 10 0 0.5
IOL-VOL1
R0~R2, R4~R6 pins
IOL (mA) VDD=3.0V TA=25C 20 15 10 5 0
IOL-VOL1
R0,R1, R4~R6 pins
1.0
1.5
2.0
2.5
VOL (V)
0.5
1.0
1.5
2.0
VOL (V)
IOL (mA) VDD=5.0V TA=25C 40 30 20 10 0 0.5
IOL-VOL2
R3 pin
IOL (mA) VDD=3.0V TA=25C 20 15 10 5 0
IOL-VOL2
R3 pin
1.0
1.5
2.0
2.5
VOL (V)
0.5
1.0
1.5
2.0
VOL (V)
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MC80F0208/16/24
IDD-VDD
IDD (mA) 10 7.5 5 2.5 TA=25C
Main Active Mode IDD (mA) 4 3
ISLEEP-VDD
TA=25C
Main Active Mode IDD (A) 4 3 2
ISTOP-VDD
TA=25C
Main Active Mode
fXIN = 12MHz
8MHz
2 fXIN = 12MHz 1
8MHz
fXIN = 12MHz, 8MHz, 4MHz 1
4MHz 0 2 3 4 5 VDD 6 (V) 0 2 3 4
4MHz 5 VDD 6 (V) 0 2 3 4 5 VDD 6 (V)
fXIN Operating Area (MHz) TA= -40~85C 16 14 12 10 8 6 4 2 0 1 2 3 4 5 6 7 VDD (V)
Actual Operating Area 2.1~7.0V @ (0.2~8MHz) 2.6~7.0V @ (0.2~16MHz)
Spec Operating Area 2.7~5.5V @ (0.4~8MHz) 4.5~5.5V @ (0.4~12MHz)
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Preliminary
8. MEMORY ORGANIZATION
The MC80F0208/16/24 has separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can be up to 48K bytes of Program memory. Data memory can be read and written to up to 1024 bytes including the stack area.
8.1 Registers
This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 100H to 1FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is used.
Bit 15 Stack Address (100H ~ 1FFH) 87 Bit 0 01H SP 00H~FFH Hardware fixed
A X Y SP PCH PCL PSW
ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD
Figure 8-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below.
Y Y A Two 8-bit Registers can be used as a "YA" 16-bit Register A
Note: The Stack Pointer must be initialized by software because its value is undefined after Reset. Example: To initialize the SP LDX #0FFH TXSP
; SP FFH
Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result.
Figure 8-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore). Generally, SP is automatically updated when a subroutine call is
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MC80F0208/16/24
PSW NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when G=1, page is selected to "page 1" BRK FLAG
MSB NVGBH
I
Z
LSB C RESET VALUE: 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G] This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned 100H to 1FFH. It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or 128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
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At execution of a CALL/TCALL/PCALL
At acceptance of interrupt
At execution of RET instruction
At execution of RET instruction
01FF 01FE 01FD 01FC
PCH PCL
Push down
01FF 01FE 01FD 01FC
PCH PCL PSW
Push down
01FF 01FE 01FD 01FC
PCH PCL
Pop up
01FF 01FE 01FD 01FC
PCH PCL PSW
Pop up
SP before execution SP after execution
01FF 01FD
01FF 01FC
01FD 01FF
01FC 01FF
At execution of PUSH instruction PUSH A (X,Y,PSW) 01FF 01FE 01FD 01FC A Push down
At execution of POP instruction POP A (X,Y,PSW) 01FF 01FE 01FD 01FC 01FFH A Pop up 0100H
Stack depth
SP before execution SP after execution
01FF 01FE
01FE 01FF
Figure 8-4 Stack Operation
8.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 32/48K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5, shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6. As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program
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MC80F0208/16/24
.
A000H
The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFCH. The interrupt service locations spaces 2-byte interval: 0FFFAH and 0FFFBH for External Interrupt 1, 0FFFCH and 0FFFDH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory.
C000H MC80F0224, 24K ROM
E000H MC80F0208, 8K ROM
MC80F0216, 16K ROM
Address 0FFE0H E2 E4 E6 E8 EA EC EE F0
Vector Area Memory Basic Interval Timer Watch / Watchdog Timer Interrupt A/D Converter Timer/Counter 4 Interrupt Timer/Counter 3 Interrupt Timer/Counter 2 Interrupt Timer/Counter 1 Interrupt Timer/Counter 0 Interrupt Serial Input/Output (SIO) UART1 Rx/Tx interrupt UART0 Rx/Tx interrupt External Interrupt 3 External Interrupt 2 External Interrupt 1 External Interrupt 0 RESET
FFC0H FFDFH FFE0H FFFFH
TCALL area Interrupt Vector Area
Figure 8-5 Program Memory Map Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7. Example: Usage of TCALL
PCALL area
FEFFH FF00H
F2 F4 F6 F8 FA FC FE
Figure 8-6 Interrupt Vector Area
LDA
#5 TCALL 0FH : :
;1BYTE INSTRUCTION ;INSTEAD OF 3 BYTES ;NORMAL CALL
; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B
1
;TCALL ADDRESS AREA
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Preliminary
Address 0FF00H
PCALL Area Memory
Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * NOTE: * means that the BRK software interrupt is using same address with TCALL0.
PCALL Area (256 Bytes)
0FFFFH
Figure 8-7 PCALL and TCALL Memory Area
PCALL rel
4F35 PCALL 35H
TCALL n
4A TCALL 4
4F 35 ~ ~
4A ~ ~ NEXT
01001010
FH FH
Reverse
~ ~
0FF00H 0FF35H NEXT
~ ~
0D125H
PC: 11111111 11010110 DH 6H
0FF00H 0FFD6H 0FFD7H 25 D1
0FFFFH
0FFFFH
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MC80F0208/16/24
Example: The usage software example of Vector address for MC80F0208/16/24 . ;Interrupt Vector Table ORG 0FFE0H DW BIT_TIMER DW WATCH_WDT DW ADC DW TIMER4 DW TIMER3 DW TIMER2 DW TIMER1 DW TIMER0 DW SIO DW UART1 DW UART0 DW INT3 DW INT2 DW INT1 DW INT0 DW RESET
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
BIT WDT & WT AD Converter Timer-4 Timer-3 Timer-2 Timer-1 Timer-0 Serial Interface UART1 Rx/Tx UART0 Rx/Tx Ext Int.3 Ext Int.2 Ext Int.1 Ext Int.0 Reset
ORG 0A000H ; 24K bytes ROM Start address ;******************************************* ; MAIN PROGRAM * ;******************************************* RESET: DI ;Disable All Interrupt RAMCLEAR: LDX #00H ;USER RAM START ADDRESS LOAD ! LDY #0 RAMCLR1: LDA #00H ;Page0 Ram Clear(0000h ~ 00BFh) STA {X}+ ; CMPX #0C0H ; BNE RAMCLR1 ; INC STY SETG LDX RAMCLR2: LDA STA CMPX BNE INC CMPY BCS STY SETG BRA RAMCLR3: STY SETG LDA STA CMPX BNE CLRG LDX TXSP #0FFH ;Initial Stack Point (01FFh) !RPR #00H {X}+ #40H RAMCLR3 ;Page4 Clear(0400h ~ 043Fh) ;A <-- #0 ; ;G-FLAG CLEAR ! #00H {X}+ #00H RAMCLR2 Y #4 RAMCLR3 !RPR RAMCLR2 Y !RPR #00H ; ;Page1 Ram Select ;G-FLAG SET !
;Page1 ~ Page3 Clear(0100h ~ 03FFh)
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Preliminary
8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into three groups, a user RAM, control registers, and Stack memory.
0000H User Memory (192Bytes) 00BFH 00C0H 00FFH 0100H Control Registers
Control Registers
The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section.
PAGE0 (When "G-flag=0", this page0 is selected)
User Memory or Stack Area (256Bytes) 01FFH 0200H User Memory (256Bytes) 02FFH 0300H 03BFH 03C0H 03FFH 0400H 043FH 0440H User Memory (256Bytes)
PAGE1
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction, for example "LDM".
PAGE2
Example; To write at CKCTLR LDM CLCTLR,#0AH ;Divide ratio(/32)
PAGE3
Stack Area
The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 22.
User Memory (64Bytes) PAGE4 Not Used
04FFH
Figure 8-8 Data Memory Map
User Memory
The MC80F0208/16/24 has 1024 x 8 bits for the user memory (RAM). RAM pages are selected by RPR (See Figure 8-9). Note: After setting RPR(RAM Page Select Register), be sure to execute SETG instruction. When executing CLRG instruction, be selected PAGE0 regardless of RPR.
7
6 -
5 -
4 -
3 -
R/W 2
R/W 1
R/W 0 ADDRESS: 0E1H INITIAL VALUE: ---- -000B System clock source select 000 : PAGE0 001 : PAGE1 010 : PAGE2 011 : PAGE3 100 : PAGE4
RPR
-
RPR2 RPR1 RPR0
Figure 8-9 RPR(RAM Page Select Register)
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MC80F0208/16/24
Address 00C0 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF 00D0
Register Name R0 port data register R0 port I/O direction register R1 port data register R1 port I/O direction register
Symbol R0 R0IO R1 R1IO Reserved Reserved
R/W R/W W R/W W
Initial Value
76543210
Addressing Mode byte, bit1 byte2 byte, bit byte
00000000 00000000 00000000 00000000
R3 port data register R3 port I/O direction register R4 port data register R4 port I/O direction register R5 port data register R5 port I/O direction register R6 port data register R6 port I/O direction register Reserved Reserved Timer 0 mode control register Timer 0 register
R3 R3IO R4 R4IO R5 R5IO R6 R6IO
R/W W R/W W R/W W R/W W
00000000 00000000 00000000 00000000 -00000 -00000
byte, bit byte byte, bit byte byte, bit byte byte, bit byte
00000000 00000000
TM0 T0 TDR0 CDR0 TM1 TDR1 T1 CDR1 Reserved
R/W R W R R/W W R R
-
-000000
byte, bit
00000000 11111111 00000000 00000000 11111111 00000000 byte 00000000 byte, bit byte byte
00D1
Timer 0 data register Timer 0 capture data register
00D2 00D3 00D4
Timer 1 mode control register Timer 1 data register Timer 1 register Timer 1 capture data register
00D5 00D6 Timer 2 mode control register Timer 2 register 00D7 Timer 2 data register Timer 2 capture data register 00D8 00D9 Timer 3 PWM period register Timer 3 mode control register Timer 3 data register
TM2 T2 TDR2 CDR2 TM3 TDR3 T3PPR
R/W R W R R/W W W
-
-000000
byte, bit
00000000 11111111 00000000 00000000 11111111 byte 11111111 byte, bit byte
Table 8-1 Control Registers
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Address
Register Name Timer 3 register
Symbol T3 T3PDR CDR3 T3PWHR TM4 T4L TDR4L CDR4L T4H TDR4H CDR4H IFR BUZR RPR SIOM SIOR Reserved Reserved
R/W R R/W R W R/W R W R R W R R/W W R/W R/W R/W
Initial Value
76543210
Addressing Mode
00000000 00000000 00000000 -0000 byte byte, bit byte
00DA
Timer 3 PWM duty register Timer 3 capture data register
00DB 00DC
Timer 3 PWM high register Timer 4 mode control register Timer 4 low register
-000000
00000000 11111111 00000000 00000000 11111111 00000000 -000000 byte, bit byte byte, bit byte, bit byte, bit byte byte
00DD
Timer 4 low data register Timer 4 capture low data register Timer 4 high register
00DE
Timer 4 high data register Timer 4 capture high data register
00DF 00E0 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8 00E9
Interrupt flag register Buzzer driver register RAM page selection register SIO mode control register SIO data shift register
11111111 -000
00000001 Undefined
UART0 mode register UART0 status register UART0 Baud rate generator control register UART0 Receive buffer register UART0 Transmit shift register
ASIMR0 ASISR0 BRGCR0 RXR0 TXR0 IENH IENL IRQH IRQL IEDS ADCM ADCRH ADCRL BITR CKCTLR Reserved
R/W R R/W R W R/W R/W R/W R/W R/W R/W R(W) R R W
0000-00-000
byte, bit byte byte, bit byte
-0010000 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00000001 01 Undefined Undefined Undefined
00EA 00EB 00EC 00ED 00EE 00EF 00F0 00F1 00F2
Interrupt enable register high Interrupt enable register low Interrupt request register high Interrupt request register low Interrupt edge selection register A/D converter mode control register A/D converter result high register A/D converter result low register Basic interval timer register Clock control register
byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte
0-010111
00F3
Table 8-1 Control Registers
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MC80F0208/16/24
Address
Register Name Watch dog timer register
Symbol WDTR WDTDR SSCR WTMR PFDR PSR0 PSR1 Reserved Reserved
R/W W R W R/W R/W W W
Initial Value
76543210
Addressing Mode byte
01111111 Undefined 00000000 0-00000 -000 byte byte, bit byte, bit byte byte
00F4 Watch dog timer data register 00F5 00F6 00F7 00F8 00F9 00FA 00FB 00FC 00FD 00FE 00FF 0EE6 0EE7 0EE8 0EE9 UART1 Transmit shift register TXR1 W 11111111 UART1 mode register UART1 status register UART1 Baud rate generator control register UART1 Receive buffer register Pull-up selection register 0 Pull-up selection register 1 Pull-up selection register 4 Reserved ASIMR1 ASISR1 BRGCR1 RXR1 R/W R R/W R 0000-00-000 Stop & sleep mode control register Watch timer mode register PFD control register Port selection register 0 Port selection register 1
00000000 -0000
PU0 PU1 PU4
W W W
00000000 00000000 00000000
byte byte byte
byte, bit byte byte, bit byte
-0010000 00000000
Table 8-1 Control Registers
1.
The `byte, bit' means registers are controlled by both bit and byte manipulation instruction. Caution) The R/W register except T1PDR and T3PDR are both can be byte and bit manipulated. The `byte' means registers are controlled by only byte manipulation instruction. Do not use bit manipulation instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. The UART1 control register ASIMR1,ASISR1, BRGCR1,RXR1 and TXR1 are located at EE6H ~ EE9H address. These address must be accessed(read and written) by absolute addressing manipulation instruction.
2.
3.
*The mark of `-' means this bit location is reserved.
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Address 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0C8H 0C9H 0CAH 0CBH 0CCH 0CDH 0CEH 0CFH 0D0H 0D1H 0D2H 0D3H 0D4H 0D5H 0D6H 0D7H 0D8H 0D9H 0DAH 0DBH 0DCH 0DDH
Name R0 R0IO R1 R1IO
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R0 Port Data Register R0 Port Direction Register R1 Port Data Register R1 Port Direction Register Reserved Reserved
R3 R3IO R4 R4IO R5 R5IO R6 R6IO
R3 Port Data Register R3 Port Direction Register R4 Port Data Register R4 Port Direction Register R5 Port Data Register R5 Port Direction Register
R6 Port Data Register R6 Port Direction Register Reserved Reserved
TM0 T0/TDR0/ CDR0 TM1 TDR1 T1/CDR1 PWM1HR TM2 T2/TDR2/ CDR2 TM3 TDR3/ T3PPR
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
Timer0 Register / Timer0 Data Register / Timer0 Capture Data Register 16BIT CAP1 T1CK1 T1CK0 T1CN T1ST
Timer1 Data Register Timer1 Register / Timer1 Capture Data Register -
Timer1 PWM High Register T2CK1 T2CK0 T2CN T2ST
-
CAP2
T2CK2
Timer2 Register / Timer2 Data Register / Timer2 Capture Data Register POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST
Timer3 Data Register / Timer3 PWM Period Register
T3/CDR3/ Timer3 Register / Timer3 Capture Data Register / Timer3 PWM Duty Register T3PDR PWM3HR TM4 T4L/ TDR4L/ CDR4L -
Timer3 PWM High Register T4CK1 T4CK0 T4CN T4ST
-
CAP4
T4CK2
Timer4 Register Low / Timer4 Data Register Low / Timer4 Capture Data Register Low
Table 8-2 Control Register Function Description
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Address 0DEH 0DFH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0E7H 0E8H 0E9H 0EAH 0EBH 0ECH 0EDH 0EEH 0EFH 0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH
Name T4H/ TDR4H/ CDR4H IFR BUZR RPR SIOM SIOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer4 Register High / Timer4 Data Register High / Timer4 Capture Data Register High BUCK1 POL BUCK0 IOSW RX0IOF BUR5 SM1 TX0IOF BUR4 SM0 RX1IOF BUR3 SCK1 TX1IOF BUR2 RPR2 SCK0 WTIOF BUR1 RPR1 SIOST WDTIOF BUR0 RPR0 SIOSF
SIO Data Shift Register Reserved Reserved
ASIMR0 ASISR0 BRGCR0 RXR0 TXR0 IENH IENL IRQH IRQL IEDS ADCM ADCRH ADCRL BITR1 CKCTLR1
TXE0 -
RXE0 TPS02
PS01 TPS01
PS00 TPS00
MLD03
SL0 PE0 MLD02
ISRM0 FE0 MLD01
OVE0 MLD00
UART0 Receive Buffer Register UART0 Transmit Shift Register INT0E T1E INT0IF T1IF IED3H ADEN PSSEL1 INT1E T2E INT1IF T2IF IED3L ADCK PSSEL0 INT2E T3E INT2IF T3IF IED2H ADS3
ADC8
INT3E T4E INT3IF T4IF IED2L ADS2
-
RXE ADCE RXIF ADCIF IED1H ADS1
-
TXE WDTE TXIF WDTIF IED1L ADS0
-
SIOE WTE SIOIF WTIF IED0H ADST
T0E BITE T0IF BITIF IED0L ADSF
ADC Result Reg. High
ADC Result Register Low Basic Interval Timer Data Register ADRST Reserved RCWDT WDTON BTCL BTS2 BTS1 BTS0
WDTR WDTDR SSCR WTMR PFDR PSR0 PSR1
WDTCL
7-bit Watchdog Timer Register
Watchdog Timer Data Register (Counter Register) Stop & Sleep Mode Control Register WTEN PWM3O Reserved Reserved EC1E WTIN2 EC0E WTIN1 INT3E XTEN WTIN0 PFDEN INT2E BUZO WTCK1 PFDM INT1E WTCK0 PFDS INT0E -
PU0 PU1 PU4
R0 Pull-up Selection Register R1 Pull-up Selection Register R4 Pull-up Selection Register Table 8-2 Control Register Function Description
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Address 0FFH EE6H2 EE7H2 EE8H2 EE9H2
Name
Bit 7 Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ASIMR1 ASISR1 BRGCR1 RXR1 TXR1
TXE1 -
RXE1 TPS12
PS11 TPS11
PS10 TPS10
MLD13
SL1 PE1 MLD12
ISRM1 FE1 MLD11
OVE1 MLD10
UART1 Receive Buffer Register UART1 Transmit Shift Register Table 8-2 Control Register Function Description
1. The register BITR and CKCTLR are located at same address. Address F2H is read as BITR, written to CKCTLR. Caution) The registers of dark-shaded area can not be accessed by bit manipulation instruction such as "SET1, CLR1", but should be accessed by register operation instruction such as "LDM dp,#imm". 2. The UART1 control register ASIMR1,ASISR1, BRGCR1,RXR1 and TXR1 are located at EE6H ~ EE9H address. These address must be accessed(read and written) by absolute addressing manipulation instruction.
8.4 Addressing Mode
The MC800 series MCU uses six addressing modes;
* Register addressing * Immediate addressing * Direct page addressing * Absolute addressing * Indexed addressing * Register-indirect addressing
When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1 E45535 LDM 35H,#55H
0135H
data
data 55H
8.4.1 Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
0F100H 0F101H 0F102H
~ ~
E4 55 35
~ ~
8.4.2 Immediate Addressing #imm
In this mode, second byte (operand) is accessed as a data immediately. Example: 0435 ADC #35H
MEMORY
8.4.3 Direct Page Addressing dp
In this mode, a address is specified within direct page. Example; G=0
04 35
A+35H+C A
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MC80F0208/16/24
C535
LDA
35H
;A RAM[35H]
983501
INC
!0135H
;A ROM[135H]
35H
data
~ ~
135H
data
~ ~
~ ~
0E550H 0E551H C5 35
data A 0F100H 0F101H 0F102H
~ ~
98 35 01
data+1 data
address: 0135
8.4.4 Absolute Addressing !abs
Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; 0735F0 ADC !0F035H ;A ROM[0F035H]
8.4.5 Indexed Addressing X indexed direct page (no offset) {X}
In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1 D4 LDA {X} ;ACCRAM[X].
115H
data
~ ~
data A
0F035H
data
~ ~
~ ~
0E550H D4
~ ~
0F100H 0F101H 0F102H 07 35 F0
A+data+C A
address: 0F035
X indexed direct page, auto increment {X}+
The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag. In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H DB LDA {X}+
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Preliminary
D500FA
LDA
!0FA00H+Y
35H
data
~ ~
data A 0F100H 0F101H 0F102H D5 00 FA
~ ~
DB
0FA00H+55H=0FA55H
36H X
~ ~
0FA55H data
~ ~

data A
X indexed direct page (8 bit offset) dp+X
This address value is the second byte (Operand) of command plus the data of X-register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H C645 LDA 45H+X JMP, CALL Example; G=0 3F35
3AH data
8.4.6 Indirect Addressing Direct page indirect [dp]
Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y.
JMP
[35H]
~ ~
0E550H 0E551H C6 45
~ ~

data A
35H 36H
0A E3
45H+0F5H=13AH 0E30AH
~ ~
NEXT
~ ~

jump to address 0E30AH
~ ~
0FA00H 3F 35
~ ~
Y indexed direct page (8 bit offset) dp+Y
This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X.
X indexed indirect [dp+X]
Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H
Y indexed absolute !abs+Y
Sets the value of 16-bit absolute address plus Y-register data as Memory.This addressing mode can specify memory in whole area. Example; Y=55H
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1625
ADC
[25H+X]
Absolute indirect [!abs]
The program jumps to address specified by 16-bit absolute address.
35H 36H
05 E0
JMP ~ 0E005H ~ Example; G=0 1F25E0 JMP [!0C025H]
~ ~
0E005H data
25 + X(10) = 35H
~ ~
PROGRAM MEMORY
~ ~
0FA00H 16 25
0E025H
25 E7
A + data + C A Y indexed indirect [dp]+Y
Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Yregister data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H 1725 ADC [25H]+Y
0E026H
~ ~
~ ~
NEXT
jump to address 0E30AH
0E725H
~ ~
0FA00H 1F 25 E0
~ ~
25H 26H
05 E0
~ ~
0E015H data
~ ~

0E005H + Y(10) = 0E015H
~ ~
0FA00H 17 25
~ ~
A + data + C A
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9. I/O PORTS
The MC80F0208/16/24 has six ports (R0, R1, R3, R4, R5 and R6). These ports pins may be multiplexed with an alternate function for the peripheral features on the device. R3 port can drive maximum 20mA of high current in output low state, so it can directly drive LED device. All pins have data direction registers which can define these ports as output or input. A "1" in the port direction register configure the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55H" to address 0C1H (R0 port direction register) during initial setting as shown in Figure 9-1. All the port direction registers in the MC80F0208/16/24 have 0 written to them by reset function. On the other hand, its initial status is input. R0 Pull-up Selection Register PU0
0C0H 0C1H 0C2H 0C3H R0 data R0 direction R1 data R1 direction I O I O I O I O PORT 76543210 I: INPUT PORT O: OUTPUT PORT 01010101 76543210 BIT Pull-up Resister Selection 0: Disable 1: Enable
R0 Data Register R0
ADDRESS: 0C0H RESET VALUE: 00H
R07 R06 R05 R04 R03 R02 R01 R00
Input / Output data
R0 Direction Register R0IO
ADDRESS: 0C1H RESET VALUE: 00H
Port Direction 0: Input 1: Output
WRITE "55H" TO PORT R0 DIRECTION REGISTER
ADDRESS: 0FCH RESET VALUE: 00H
Figure 9-1 Example of port I/O assignment
R0 and R0IO register: R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0IO register (address 0C1H). The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 0 (PU0).
R1 and R1IO register: R1 is an 5-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R1IO register (address 0C3H). The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 1 (PU1). In addition, Port R1 is multiplexed with various special features. The control register PSR0 (address 0F8H) and PSR1 (address 0F9H) controls the selection of alternate function. After reset, this value is "0", port may be used as normal I/O port. To use alternate function such as external interrupt, event counter input or timer clock output, write "1" in the corresponding bit of PSR0 or PSR1. Regardless of the direction register R1IO, PSR0 or PSR1 is selected to use as alternate functions, port pin can be used as a corresponding alternate features. Port Pin R10 R11 R12 R13 R15 Alternate Function INT0 (External Interrupt 0) INT1 (External Interrupt 1) INT2 (External Interrupt 2) BUZO (Square-wave output for buzzer) EC0 (Event counter input to Counter 0)
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port (address 0C6H). Each I/O pin can independently used as an input or an output through the R3IO register (address 0C7H). R1 Data Register R1
R15 ADDRESS: 0C2H RESET VALUE: 00H R13 R12 R11 R10
In addition, Port R3 is multiplexed with various special features. After reset, this value is "0", port may be used as normal I/O port.
Input / Output data
Port Pin R30 R31 R32 R33
Alternate Function ACLK1 (UART1 clock input) RxD1 (UART1 data input) TxD1(UART1 data output)
R1 Direction Register R1IO
-
ADDRESS: 0C3H RESET VALUE: 00H
Port Direction 0: Input 1: Output
R3 Data Register R1 Pull-up Selection Register PU1
ADDRESS: 0FDH RESET VALUE: 00H
ADDRESS: 0C6H RESET VALUE: 00H R33 R32 R31 R30
R3
-
-
Input / Output data Pull-up Resister Selection 0: Disable 1: Enable
R3 Direction Register R3IO
-
ADDRESS: 0C7H RESET VALUE: 00H
ADDRESS: 0F8H RESET VALUE: 0-00 0000B
PSR0
PWM3O
-
EC1E EC0E INT3E INT2E INT1E INT0E
Port Direction 0: Input 1: Output
Port / INT Selection 0: R10, R11,R12, R50 1: INT0, INT1,INT2, INT3 Port / EC Selection 0: R15, R51 1: EC0, EC1 Port / PWM3 Selection 0: R54 1: PWM3O/T3O port
R4 and R4IO register: R4 is an 8-bit CMOS bidirectional I/O port (address 0C8H). Each I/O pin can independently used as an input or an output through the R4IO register (address 0C9H). The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 4 (PU4). In addition, Port R4 is multiplexed with various special features. After reset, this value is "0", port may be used as normal I/O port.
ADDRESS: 0F9H RESET VALUE: ---- -0--B
PSR1
-
-
-
-
-
BUZO
-
-
Port Pin R40 R41 R42 R43 R44 R45 R46 R47
Alternate Function SCK (SIO clock input/output) SI (SIO data input) SO (Serial1 data output) ACLK0 (UART0 clock input) RxD0 (UART0 data input) TxD0 (UART0 data output)
R13/BUZO Selection 0: R13 port (Turn off buzzer) 1: BUZO port (Turn on buzzer)
R3 and R3IO register: R3 is an 4-bit CMOS bidirectional I/O
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R4 Data Register R4
ADDRESS: 0C8H RESET VALUE: 00H
R5 Data Register R5
R54 -
ADDRESS: 0CAH RESET VALUE: ---00000B R51 R50
R47 R46 R45 R44 R43 R42 R41 R40
Input / Output data
Input / Output data
R4 Direction Register R4IO
ADDRESS: 0C9H RESET VALUE: 00H
R5 Direction Register R5IO
-
ADDRESS: 0CBH RESET VALUE: ---00000B -
Port Direction 0: Input 1: Output
Port Direction 0: Input 1: Output ADDRESS: 0F8H RESET VALUE: 0-00 0000B
R4 Pull-up Selection Register PU4
ADDRESS: 0FEH RESET VALUE: 00H
PSR0
Pull-up Resister Selection 0: Disable 1: Enable
PWM3O
-
EC1E EC0E INT3E INT2E INT1E INT0E
Port / INT Selection 0: R10, R11, R12, R50 1: INT0, INT1, INT2, INT3 Port / EC Selection 0: R15, R51 1: EC0, EC1
R5 and R5IO register: R5 is an 3-bit CMOS bidirectional I/O port (address 0CAH). Each I/O pin can independently used as an input or an output through the R5IO register (address 0CBH). In addition, Port R5 is multiplexed with various special features. The control register PSR0 (address 0F8H) and PSR1 (address 0F9H) controls the selection of alternate function. After reset, this value is "0", port may be used as normal I/O port. To use alternate function such as external interrupt, event counter input, timer clock output or PWM output, write "1" in the corresponding bit of PSR0 or PSR1. Regardless of the direction register R5IO, PSR0 or PSR1 is selected to use as alternate functions, port pin can be used as a corresponding alternate features. Port Pin R50 R51 R54 Alternate Function INT3 (External Interrupt 3) EC1 (Event counter input to Counter 2) PWM3O (PWM3/T3O output)
Port / PWM3 Selection 0: R54 1: PWM3O/T3O port
R6 and R6IO register: R6 is an 8-bit CMOS bidirectional I/O port (address 0CCH). Each I/O pin can independently used as an input or an output through the R6IO register (address 0CDH). In addition, Port R6 is multiplexed with AD converter analog input AN0~AN7. Port Pin R60 R61 R62 R63 R64 R65 R66 R67 Alternate Function AN0 (ADC input channel 0) AN1 (ADC input channel 1) AN2 (ADC input channel 2) AN3 (ADC input channel 3) AN4 (ADC input channel 4) AN5 (ADC input channel 5) AN6 (ADC input channel 6) AN7 (ADC input channel 7)
R6IO (address CDH) controls the direction of the R6 pins, except when they are being used as analog input channels. The user don't have to keep the pins configured as inputs when using them as analog input channels, because the analog input mode is activated by the setting of ADC enable bit of ADCM register and ADC
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channel selection . R6 Data Register R6
ADDRESS: 0CCH RESET VALUE: 00H
R67 R66 R65 R64 R63 R62 R61 R60 Input / Output data
R6 Direction Register R6IO
ADDRESS: 0CDH RESET VALUE: 00H
Port Direction 0: Input 1: Output
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10. CLOCK GENERATOR
As shown in Figure 10-1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main-frequency clock oscillator. The system clock operation can be easily obtained by attaching a crystal or a ceramic resonator between the XIN and XOUT pin, respectively. The system clock can also be obtained from the external oscillator. In this case, it is necessary to input a external clock signal to the XIN pin and open the XOUT pin. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. To the peripheral block, the clock among the not-divided original clock, clocks divided by 1, 2, 4,..., up to 4096 can be provided. Peripheral clock is enabled or disabled by STOP instruction. The peripheral clock is controlled by clock control register (CKCTLR). See "11. BASIC INTERVAL TIMER" on page 41 for details.
STOP SLEEP
Main OSC Stop
XIN XOUT
OSC Circuit
fEX
Clock Pulse Generator (/2)
Internal system clock
PRESCALER
PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12
/1
/2
/4
/8
/16
/32
/64
/128
/256
/512 /1024 /2048 /4096
Peripheral clock
fEX (Hz)
Frequency 4M period
PS0 4M 250n
PS1 2M 500n
PS2 1M 1u
PS3 500K 2u
PS4 250K 4u
PS5 125K 8u
PS6 62.5K 16u
PS7 31.25K 32u
PS8 15.63K 64u
PS9 7.183K 128u
PS10 3.906K 256u
PS11 1.953K 512u
PS12 976 1.024m
Figure 10-1 Block Diagram of Clock Generator
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11. BASIC INTERVAL TIMER
The MC80F0208/16/24 has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Figure 111. In addition, the Basic Interval Timer generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BITIF). The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 10-2. When write "1" to bit BTCL of CKCTLR, BITR register is cleared to "0" and restart to count-up. The bit BTCL becomes "0" after one machine cycle by hardware. If the STOP instruction executed after writing "1" to bit RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and Watchdog Timer. More detail informations are explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer. Source clock can be selected by lower 3 bits of CKCTLR. BITR and CKCTLR are located at same address, and address 0F2H is read as a BITR, and written to CKCTLR.
Internal RC OSC
RCWDT
/8 /16 /32
1
source clock
8-bit up-counter overflow BITR BITIF
Basic Interval Timer Interrupt
Prescaler
/64 /128 /256 /512 /1024
MUX
0 [0F2H] clear To Watchdog timer (WDTCK)
XIN PIN
Select Input clock 3 BTS[2:0] [0F2H] Basic Interval Timer clock control register Internal bus line CKCTLR Read RCWDT BTCL
Figure 11-1 Block Diagram of Basic Interval Timer
CKCTLR [2:0] 000 001 010 011 100 101 110 111
Source clock fXIN/8 fXIN/16 fXIN/32 fXIN/64 fXIN/128 fXIN/256 fXIN/512 fXIN/1024
Interrupt (overflow) Period (ms) @ fXIN = 8MHz 0.256 0.512 1.024 2.048 4.096 8.192 16.384 32.768
Table 11-1 Basic Interval Timer Interrupt Period
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7
CKCTLR
ADRST
6 -
5
4
3
2
1
0
RCWDT WDTONBTCL BTCL
BTS2 BTS1 BTS0
ADDRESS: 0F2H INITIAL VALUE: 0-01 0111B
Basic Interval Timer source clock select 000: fXIN / 8 001: fXIN / 16 010: fXIN / 32 011: fXIN / 64 100: fXIN / 128 101: fXIN / 256 110: fXIN / 512 111: fXIN / 1024 Clear bit 0: Normal operation (free-run) 1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically after one machine cycle, and starts counting. Watchdog timer Enable bit 0: Operate as 7-bit Timer 1: Enable Watchdog Timer operation See the section "Watchdog Timer". RC Watchdog Selection bit 0: Disable Internal RC Watchdog Timer 1: Enable Internal RC Watchdog Timer Address Trap Reset Selection 0: Enable Address Fail Reset 1: Disable Address Fail Reset
Caution:
Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR.
7
6
5
4
BITR
3 BTCL
2
1
0
ADDRESS: 0F2H INITIAL VALUE: Undefined
8-BIT FREE-RUN BINARY COUNTER
Figure 11-2 BITR: Basic Interval Timer Mode Register Example 1: Interrupt request flag is generated every 8.192ms at 4MHz. : LDM SET1 EI : CKCTLR,#1BH BITE Example 2: Interrupt request flag is generated every 8.192ms at 8MHz. : LDM SET1 EI : CKCTLR,#1CH BITE
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12. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external oscillator of the XIN pin. It means that the watchdog timer will run, even if the clock on the XIN pin of the device has been stopped, for example, by entering the STOP mode. The other type is a prescaled system clock. The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as Watchdog timer interrupt or reset the CPU in accordance with the bit WDTON. Note: Because the watchdog timer counter is enabled after clearing Basic Interval Timer, after the bit WDTON set to "1", maximum error of timer is depend on prescaler ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 machine cycle. The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below. LDM LDM LDM STOP NOP NOP : CKCTLR,#3FH; enable the RC-OSC WDT WDTR,#0FFH ; set the WDT period SSCR, #5AH ;ready for STOP mode ; enter the STOP mode ; RC-OSC WDT running
The RC-WDT oscillation period is vary with temperature, VDD and process variations from part to part (approximately, 33~100uS). The following equation shows the RCWDT oscillated watchdog timer time-out. TRCWDT=CLKRCWDTx28xWDTR + (CLKRCWDTx28)/2 where, CLKRCWDT = 33~100uS In addition, this watchdog timer can be used as a simple 7-bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. TWDT = (WDTR+1) x Interval of BIT
clear BASIC INTERVAL TIMER OVERFLOW Watchdog Counter (7-bit) clear
Count source
"0" comparator WDTCL 7-bit compare data 7 WDTR [0F4H] Internal bus line Watchdog Timer Register "1" enable
to reset CPU
WDTON in CKCTLR [0F2H] WDTIF Watchdog Timer interrupt
Figure 12-1 Block Diagram of Watchdog Timer
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Watchdog Timer Control
Figure 12-2 shows the watchdog timer control register. The watchdog timer is automatically disabled after reset. The CPU malfunction is detected during setting of the detection time, selecting of output, and clearing of the binary counter. Clearing the binary counter is repeated within the detection time. If the malfunction occurs for any cause, the watchdog timer output will become active at the rising overflow from the binary
W 7 W 6 W 5 W 4 W 3 W 2
counters unless the binary counter is cleared. At this time, when WDTON=1, a reset is generated, which drives the RESET pin to low to reset the internal hardware. When WDTON=0, a watchdog timer interrupt (WDTIF) is generated. The WDTON bit is in register CLKCTLR. The watchdog timer temporarily stops counting in the STOP mode, and when the STOP mode is released, it automatically restarts (continues counting).
W 1
W 0
WDTR
WDTCL
ADDRESS: 0F4H INITIAL VALUE: 0111 1111B
7-bit compare data Clear count flag 0: Free-run count 1: When the WDTCL is set to "1", binary counter is cleared to "0". And the WDTCL becomes "0" automatically after one machine cycle. Counter count up again.
Figure 12-2 WDTR: Watchdog Timer Control Register Example: Sets the watchdog timer detection time to 1 sec. at 4.194304MHz LDM LDM LDM : : : : LDM : : : : LDM CKCTLR,#3FH WDTR,#08FH WDTR,#08FH ;Select 1/1024 clock source, WDTON 1, Clear Counter ;Clear counter
Within WDT detection time
WDTR,#08FH
;Clear counter
Within WDT detection time
WDTR,#08FH
;Clear counter
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 4 in CKCTLR) to "1". WDTON is initialized to "0" during reset and it should be set to "1" to operate after reset is released. Example: Enables watchdog timer for Reset : LDM : : CKCTLR,#xxx1_xxxxB;WDTON 1
Watchdog Timer Interrupt
The watchdog timer can be also used as a simple 7-bit timer by clearing bit4 of CKCTLR to "0". The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below. TWDT = (WDTR+1) x Interval of BIT The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source. Example: 7-bit timer interrupt set up. LDM LDM : CKCTLR,#xxx0_xxxxB;WDTON 0 WDTR,#8FH ;WDTCL 1
The watchdog timer is disabled by clearing bit 4 (WDTON) of CKCTLR. The watchdog timer is halted in STOP mode and restarts automatically after STOP mode is released.
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Source clock BIT overflow Binary-counter
1 2 3 0 Counter Clear 1 2 3 0 Counter Clear 3 Match Detect
WDTR WDTIF interrupt
n
WDTR "1000_0011B" WDT reset reset
Figure 12-3 Watchdog timer Timing If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to reset the internal hardware. The main clock oscillator also turns on when a watchdog timer reset is generated in sub clock mode. The WDTIF bit of IFR register is set when watchdog timer interrupt is generated. (Refer to Figure 12-4)
R/W
R/W
R/W
R/W
R/W
WTIOF
R/W
WDTIOF
IFR
MSB
-
-
RX0IOF TX0IOF
RX1IOF TX1IOF
ADDRESS: 0DFH INITIAL VALUE: --00 0000B WDT interrupt occurred flagNOTE1 WT interrupt occurred flagNOTE1 UART1 Tx interrupt occurred flagNOTE2 UART1 Rx interrupt occurred flagNOTE2 UART0 Tx interrupt occurred flagNOTE3 UART0 Rx interrupt occurred flagNOTE3
LSB
NOTE1 : In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. NOTE2 : In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. NOTE3 : In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register.
Figure 12-4 IFR(Interrupt Flag Register)
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13. WATCH TIMER
The watch timer generates interrupt for watch operation. The watch timer consists of the clock selector, 15-bit binary counter, interval selector and watch timer mode register. It is a multi-purpose timer. It is generally used for watch design. The bit 0,1 of WTMR select the clock source of watch timer among fXIN/2, fXIN/27 and main-clock(fXIN). The fXIN of mainclock is used usually for watch timer test, so generally it is not used for the clock source of watch timer. The fXIN/27 of mainclock(4.194MHz) is used when the single clock system is organized. In fXIN/27 clock source, if the CPU enters into stop mode, the main-clock is stopped and then watch timer is also stopped. The watch timer counter can output with period of max 1 seconds at sub-clock. The bit 2, 3, 4 of WTMR select the interrupt interval divide ratio selection of watch timer among 16, 64, 256, 1024, 4096, 8192, 16384 or 32768. The WTIF bit of IFR register is set when watch timer interrupt is generated. (Refer to Figure 12-4)
WTMR (Watch Timer Mode Register)
W 7 WTEN R/W 4 WTIN2 R/W 3 WTIN1 R/W 2 WTIN0 R/W 1 WTCK1 R/W 0 WTCK0
6 -
5 -
ADDRESS: 0F6H INITIAL VALUE:0--0 0000B
WTEN (Watch Timer Enable) 0: Watch Timer disable 1: Watch Timer Enable
Watch Timer Clock Source selection 00: 01: fXIN / 128 10: fXIN 11: fXIN / 2 Watch Timer Interrupt Interval selection 000: Clock Source / 32768 001: Clock Source / 16384 010: Clock Source / 8192 011: Clock Source / 4096 100: Clock Source / 1024 101: Clock Source / 256 110: Clock Source / 64 111: Clock Source / 16
Figure 13-1 Watch Timer Mode Register
WTIN[2:0]
WTCK[1:0]
/32768 15-bit binary counter /16384 /8192 /4096 /1024 /256 /64 /16 interval selector
MUX Watch Timer interrupt
fXIN/128 fXIN fXIN/2
01 10 11 MUX
Clock Source Selector
WTEN Clear If WTEN=0
Figure 13-2 Watch Timer Block Diagram
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
14. TIMER/EVENT COUNTER
The MC80F0208/16/24 has five Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 are can be used either two 8-bit Timer/ Counter or one 16-bit Timer/Counter with combine them. Also Timer 2 and Timer 3 are same. Timer 4 is 16-bit Timer/Counter. In the "timer" function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency. In the "counter" function, the register is increased in response to a 0-to-1 (rising edge) transition at its corresponding external input pin, EC0 or EC1. In addition the "capture" function, the register is increased in response external or internal clock sources same with timer or counter function. When external clock edge input, the count register is captured into Timer data register correspondingly. When T0CK [2:0] XXX 111 XXX XXX 111 XXX T1CK [1:0] XX XX XX 11 11 11 external clock edge input, the count register is captured into capture data register CDRx. Timer 0 and Timer 1 has four operating modes: "8-bit timer/ counter", "16-bit timer/counter", "8-bit capture" and "16-bit capture" which are selected by bit in Timer mode register TM0 and TM1 as shown in Table 14-1, Figure 14-1. Timer 2 and Timer 3 is shared with "PWM" function and "Compare output" function. It has six operating modes: "8bit timer/counter", "16-bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", and "10-bit PWM" which are selected by bit in Timer mode register TM2 and TM3 as shown in Table 14-2, Figure 14-2. Timer 4 has two operating modes: "16-bit timer/counter" and "16-bit capture" which are selected by bit in Timer mode register TM4 as shown inTable 14-3, and Figure 14-3.
16BIT 0 0 0 1 1 1
CAP0 0 0 1 0 0 1
CAP1 0 1 0 0 0 1
TIMER 0 8-bit Timer 8-bit Event counter 8-bit Capture (internal clock) 16-bit Timer 16-bit Event counter 16-bit Capture (internal clock)
TIMER 1 8-bit Timer 8-bit Capture 8-bit Timer
Table 14-1 Operating Modes of Timer 0, 1
1. X means the value of "0" or "1" corresponds to user operation.
16BIT 0 0 0 0 1 1 1
CAP2 0 0 1 X 0 0 1
CAP3 0 1 0 0 0 0 1
PWM3E 0 0 0 1 0 0 0
T2CK [2:0] XXX 111 XXX XXX XXX 111 XXX
T3CK [1:0] XX XX XX XX 11 11 11
PWM3O 0 0 1 1 0 0 0
TIMER 2 8-bit Timer 8-bit Event counter 8-bit Capture (internal clock) 8-bit Timer/Counter 16-bit Timer 16-bit Event counter 16-bit Capture (internal clock)
TIMER 3 8-bit Timer 8-bit Capture 8-bit Compare Output 10-bit PWM
Table 14-2 Operating Modes of Timer 2, 3
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
CAP4 0 1
T4CK[2:0] XXX XXX 16-bit Timer
TIMER 4
16-bit Capture (internal clock)
Table 14-3 Operating Modes of Timer 4
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 T0ST
TM0
-
-
CAP0 T0CK2 T0CK1 T0CK0 T0CN BTCL
ADDRESS: 0D0H INITIAL VALUE: --00 0000B
Bit Name CAP0 T0CK2 T0CK1 T0CK0
Bit Position TM0.5 TM0.4 TM0.3 TM0.2
Description 0: Timer/Counter mode 1: Capture mode selection flag 000: 8-bit Timer, Clock source is fXIN / 2 001: 8-bit Timer, Clock source is fXIN / 4 010: 8-bit Timer, Clock source is fXIN / 8 011: 8-bit Timer, Clock source is fXIN / 32 100: 8-bit Timer, Clock source is fXIN / 128 101: 8-bit Timer, Clock source is fXIN / 512 110: 8-bit Timer, Clock source is fXIN / 2048 111: EC0 (External clock) 0: Timer count pause 1: Timer count start 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again.
T0CN T0ST
TM0.1 TM0.0
7
R/W 6 16BIT
5
-
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0
TM1
-
CAP1 T1CK1 T1CK0 T1CN T1ST BTCL
ADDRESS: 0D2H INITIAL VALUE: -0-0 0000B
Bit Name 16BIT CAP1 T1CK1 T1CK0
Bit Position TM1.6 TM1.4 TM1.3 TM1.2
Description 0: 8-bit Mode 1: 16-bit Mode 0: Timer/Counter mode 1: Capture mode selection flag 00: 8-bit Timer, Clock source is fXIN 01: 8-bit Timer, Clock source is fXIN / 2 10: 8-bit Timer, Clock source is fXIN / 8 11: 8-bit Timer, Clock source is Using the Timer 0 Clock 0: Timer count pause 1: Timer count start 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again.
T1CN T1ST
TM1.1 TM1.0
R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0
TDR0
R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0
ADDRESS: 0D1H INITIAL VALUE: 0FFH ADDRESS: 0D3H INITIAL VALUE: 0FFH
TDR1
Read: Count value read Write: Compare data write
Figure 14-1 TM0, TM1 Registers
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 T2ST
TM2
-
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN BTCL
ADDRESS: 0D6H INITIAL VALUE: --00 0000B
Bit Name CAP2 T2CK2 T2CK1 T2CK0
Bit Position TM2.5 TM2.4 TM2.3 TM2.2
Description 0: Timer/Counter mode 1: Capture mode selection flag 000: 8-bit Timer, Clock source is fXIN / 2 001: 8-bit Timer, Clock source is fXIN / 4 010: 8-bit Timer, Clock source is fXIN / 8 011: 8-bit Timer, Clock source is fXIN / 16 100: 8-bit Timer, Clock source is fXIN / 64 101: 8-bit Timer, Clock source is fXIN / 256 110: 8-bit Timer, Clock source is fXIN / 1024 111: EC1 (External clock) 0: Timer count pause 1: Timer count start 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again.
T2CN T2ST
TM2.1 TM2.0
R/W 7
R/W 6
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0
TM3
POL
16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL
ADDRESS: 0D8H INITIAL VALUE: 00H
Bit Name POL 16BIT PWM3E CAP3 T3CK1 T3CK0
Bit Position TM3.7 TM3.6 TM3.5 TM3.4 TM3.3 TM3.2
Description 0: PWM Duty Active Low 1: PWM Duty Active High 0: 8-bit Mode 1: 16-bit Mode 0: Disable PWM 1: Enable PWM 0: Timer/Counter mode 1: Capture mode selection flag 00: 8-bit Timer, Clock source is fXIN 01: 8-bit Timer, Clock source is fXIN / 4 10: 8-bit Timer, Clock source is fXIN / 16 11: 8-bit Timer, Clock source is Using the Timer 2 Clock 0: Timer count pause 1: Timer count start 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again.
T3CN T3ST
TM3.1 TM3.0
R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0
TDR2
R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0
ADDRESS: 0D7H INITIAL VALUE: 0FFH ADDRESS: 0D9H INITIAL VALUE: 0FFH
TDR3
Read: Count value read Write: Compare data write
Figure 14-2 TM2, TM3 Registers
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 T4ST
TM4
-
-
CAP4 T4CK2 T4CK1 T4CK0 T4CN BTCL
ADDRESS: 0DCH INITIAL VALUE: --00 0000B
Bit Name CAP4 T4CK2 T4CK1 T4CK0
Bit Position TM4.5 TM4.4 TM4.3 TM4.2
Description 0: Timer/Counter mode 1: Capture mode selection flag 000: 8-bit Timer, Clock source is fXIN / 2 001: 8-bit Timer, Clock source is fXIN / 4 010: 8-bit Timer, Clock source is fXIN / 8 011: 8-bit Timer, Clock source is fXIN / 16 100: 8-bit Timer, Clock source is fXIN / 64 101: 8-bit Timer, Clock source is fXIN / 256 110: 8-bit Timer, Clock source is fXIN / 1024 111: 8-bit Timer, Clock source is fXIN / 2048 0: Timer count pause 1: Timer count start 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again.
T4CN T4ST
TM4.1 TM4.0
R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0
TDR4H
R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0
ADDRESS: 0DDH INITIAL VALUE: 0FFH ADDRESS: 0DEH INITIAL VALUE: 0FFH
TDR4L
Figure 14-3 TM4 Register
14.1 8-bit Timer / Counter Mode
The MC80F0208/16/24 has four 8-bit Timer/Counters, Timer 0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 are shown in Figure 14-4 and Timer 2, Timer 3 are shown in Figure 14-5. The "timer" or "counter" function is selected by control registers TM0, TM1, TM2, TM3 as shown in Figure 14-1. To use as an 8bit timer/counter mode, bit CAP0, CAP1, CAP2, or CAP3 of TMx should be cleared to "0" and 16BIT of TM1 or TM3 should be cleared to "0"(Figure 14-4). These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 or external clock (selected by control bits TxCK0, TxCK1, TxCK2 of register TMx).
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
7
6 -
5
4
3
2
1
0
TM0
-
CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST BTCL 0 X X X X X
ADDRESS: 0D0H INITIAL VALUE: --00 0000B
X means don't care 7 6 16BIT 0 5
-
4
3
2
1
0
TM1
-
CAP1 T1CK1 T1CK0 T1CN T1ST BTCL 0 X X X X
ADDRESS: 0D2H INITIAL VALUE: -0-0 0000B
-
X means don't care
T0CK[2:0] EDGE DETECTOR
EC0 PIN
/2 /4 Prescaler /8 / 32 / 128 / 512 / 2048
111 T0ST 000 001 010 011 100 101 110 MUX T0CN Comparator T0IF 0: Stop 1: Clear and start T0 (8-bit) clear TIMER 0 INTERRUPT
XIN PIN
TIMER 0
TDR0 (8-bit)
T1CK[1:0] T1ST /1 /2 /8 11 00 01 10 T1CN MUX Comparator T1IF T1 (8-bit) clear TIMER 1 INTERRUPT 0: Stop 1: Clear and start
TIMER 1
TDR1 (8-bit)
Figure 14-4 8-bit Timer/Counter 0, 1
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
7
6 -
5
4
3
2
1
0
TM2
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST BTCL 0 X X X X X
ADDRESS: 0D6H INITIAL VALUE: --000000B
X means don't care 7 6 5 4 3 2 1 0
TM3
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL X 0 0 0 X X X X
ADDRESS: 0D8H INITIAL VALUE: 00H
X means don't care
T2CK[2:0] EDGE DETECTOR
EC1 PIN
/2 /4 Prescaler /8 / 16 / 64 / 256 / 1024
111 T2ST 000 001 010 011 100 101 110 MUX T2CN Comparator T2IF 0: Stop 1: Clear and start T2 (8-bit) clear TIMER 2 INTERRUPT
XIN PIN
TIMER 2
TDR2 (8-bit)
T3CK[1:0] T3ST /1 /4 / 16 11 00 01 10 T3CN MUX Comparator T3IF T3 (8-bit) clear TIMER 3 INTERRUPT 0: Stop 1: Clear and start
TIMER 3
TDR3 (8-bit)
F/F
R54/PWM3O/T3O
Figure 14-5 8-bit Timer/Counter 2, 3
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
Example 1: Timer0 = 2ms 8-bit timer mode at 4MHz Timer1 = 0.5ms 8-bit timer mode at 4MHz Timer2 = 1ms 8-bit timer mode at 4MHz Timer3 = 1ms 8-bit timer mode at 4MHz LDM LDM LDM LDM LDM LDM LDM LDM SET1 SET1 SET1 SET1 EI Example 2: Timer0 = 8-bit event counter mode Timer1 = 0.5ms 8-bit timer mode at 4MHz Timer2 = 8-bit event counter mode Timer3 = 1ms 8-bit timer mode at 4MHz LDM LDM LDM LDM LDM LDM LDM LDM SET1 SET1 SET1 SET1 EI TDR0,#249 TDR1,#249 TDR2,#249 TDR3,#249 TM0,#0001_1111B TM1,#0000_1011B TM2,#0001_1111B TM3,#0000_1011B T0E T1E T2E T3E TDR0,#249 TDR1,#249 TDR2,#249 TDR3,#249 TM0,#0000_1111B TM1,#0000_1011B TM2,#0000_1111B TM3,#0000_1011B T0E T1E T2E T3E
These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32, 128, 512, 2048 selected by control bits T0CK[2:0] of register TM0 or 1, 2, 8 selected by control bits T1CK[1:0] of register TM1, or 2, 4, 8, 16, 64, 256, 1024 selected by control bits T2CK[2:0] of register TM2, or 1, 4, 16 selected by control bits T3CK[1:0] of register TM3. In the Timer 0, timer register T0 increases from 00H until it matches TDR0 and then reset to 00H. The match output of Timer 0 generates Timer 0 interrupt (latched in T0IF bit). In counter function, the counter is increased every 0-to-1(1-to-0) (rising & falling edge) transition of EC0 pin. In order to use counter function, the bit EC0 of the Port Selection Register(PSR0.4) is set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not. Likewise, In order to use Timer2 as counter function, the bit EC1 of the Port Selection Register(PSR0.5) is set to "1". The Timer 2 can be used as a counter by pin EC1 input, but Timer 3 can not.
14.1.1 8-bit Timer Mode
In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn are compared with the contents of up-counter, Tn. If match is found, a timer n interrupt (TnIF) is generated and the up-counter is cleared to 0. Counting up is resumed after the up-counter is cleared. As the value of TDRn is changeable by software, time interval is set as you want.
Start count
Source clock
~ ~ ~ ~ n-2 ~ ~ n-1 n 1 2 3 4
Up-counter
0
1
2
3
0
TDR1 T1IF interrupt
n ~ ~ Match Detect ~ ~ Counter Clear
Figure 14-6 Timer Mode Timing Chart
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
Example: Make 1ms interrupt using by Timer0 at 4MHz LDM LDM SET1 EI
When
TM0,#0FH TDR0,#124 T0E
; ; ; ;
divide by 32 8us x (124+1)= 1ms Enable Timer 0 Interrupt Enable Master Interrupt
TM0 = 0000 1111B (8-bit Timer mode, Prescaler divide ratio = 32) TDR0 = 124D = 7CH fXIN = 4 MHz 1 INTERRUPT PERIOD = x 32 x (124+1) = 1 ms 4 x 106 Hz TDR0 7C
nt
MATCH (TDR0 = T0) 7C 7B 7A
~~
Count Pulse Period
~~
up -c
8 s
ou ~~
6 5 4 3 2 1
0
0 Interrupt period = 8 s x (124+1)
TIME
Timer 0 (T0IF) Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 14-7 Timer Count Example
14.1.2 8-bit Event Counter Mode
In this mode, counting up is started by an external trigger. This trigger means rising edge of the EC0 or EC1 pin input. Source clock is used as an internal clock selected with timer mode register TM0 or TM2. The contents of timer data register TDRn (n = 0,1,2,3) are compared with the contents of the up-counter Tn. If a match is found, an timer interrupt request flag TnIF is generated, and the counter is cleared to "0". The counter is restart and count up continuously by every falling edge of the EC0 or EC1 pin input. The maximum frequency applied to the EC0 or EC1 pin is fXIN/2 [Hz].
Start count ECn pin input
In order to use event counter function, the bit 4, 5 of the Port Selection Register PSR0(address 0F8H) is required to be set to "1". After reset, the value of timer data register TDRn is initialized to "0", The interval period of Timer is calculated as below equation.
1 Period (sec) = ---------- x 2 x Divide Ratio x (TDRn+1) f XIN
~ ~ ~ ~
Up-counter TDR1 T1IF interrupt
0 n
1
2
n-1
n
0
1
2
Figure 14-8 Event Counter Mode Timing Chart
~ ~ ~ ~ ~ ~ ~ ~
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
TDR1 disable enable
clear & start stop
up
-c
ou
nt
~ ~
~ ~
TIME
Timer 1 (T1IF) Interrupt Occur interrupt T1ST Start & Stop T1ST = 0 T1CN Control count T1CN = 0 T1CN = 1 Occur interrupt
T1ST = 1
Figure 14-9 Count Operation of Timer / Event counter
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
14.2 16-bit Timer / Counter Mode
The Timer register is being run with all 16 bits. A 16-bit timer/ counter register T0, T1 are incremented from 0000H until it matches TDR0, TDR1 and then resets to 0000H. The match output generates Timer 0 interrupt. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0]. In 16-bit mode, the bits T1CK[1:0] and 16BIT of TM1 should be set to "1" respectively as shown in Figure 14-10. Likewise, A 16-bit timer/counter register T2, T3 are incremented from 0000H until it matches TDR2, TDR3 and then resets to 0000H. The match output generates Timer 2 interrupt. The clock source of the Timer 2 is selected either internal or external clock by bit T2CK[2:0]. In 16-bit mode, the bits T3CK[1:0] and 16BIT of TM3 should be set to "1" respectively as shown in Figure 14-11. Even if the Timer 0 (including Timer 1) is used as a 16-bit timer, the Timer 2 and Timer 3 can still be used as either two 8-bit timer or one 16-bit timer by setting the TM2. Reversely, even if the Timer 2 (including Timer 3) is used as a 16-bit timer, the Timer 0 and Timer 1 can still be used as 8-bit timer independently. A 16-bit timer/counter 4 register T4H, T4L are increased from 0000H until it matches TDR4H, TDR4L and then resets to 0000H. The match output generates Timer 4 interrupt. Timer/Counter 4 is 16 bit mode as shown in Figure 14-12.
7
6 -
5
4
3
2
1
0
TM0
-
BTCL CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST 0 X X X X X
ADDRESS: 0D0H INITIAL VALUE: --00 0000B
X means don't care 7 6 16BIT 1 5
-
4
3
2
1
0
TM1
-
CAP1 T1CK1 T1CK0 T1CN T1ST BTCL 0 1 1 X X
ADDRESS: 0D2H INITIAL VALUE: -0-0 0000B
-
X means don't care T0CK[2:0] EDGE DETECTOR
EC0 PIN
/2
111 000 001 010 011 100 101 110 MUX TDR1 + TDR0 (16-bit) Higher byte Lower byte COMPARE DATA TIMER 0 + TIMER 1 TIMER 0 (16-bit) T0CN Comparator T1 + T0 (16-bit) clear TIMER 0 INTERRUPT (Not Timer 1 interrupt) T0ST 0: Stop 1: Clear and start
XIN PIN
Prescaler
/4 /8 / 32 / 128 / 512 / 2048
T0IF
Figure 14-10 16-bit Timer/Counter for Timer 0, 1
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
7
6 -
5
4
3
2
1
0
TM2
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST BTCL 0 X X X X X
ADDRESS: 0D6H INITIAL VALUE: --000000B
X means don't care 7 6 5 4 3 2 1 0
TM3
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL X 1 0 0 1 1 X X
ADDRESS: 0D8H INITIAL VALUE: 00H
X means don't care T2CK[2:0] EDGE DETECTOR
EC1 PIN
/2
111 000 001 010 011 100 101 110 MUX TDR3 + TDR2 (16-bit) Higher byte Lower byte COMPARE DATA TIMER 2 + TIMER 3 TIMER 2 (16-bit) T2CN Comparator T3 + T2 (16-bit) clear TIMER 2 INTERRUPT (Not Timer 3 interrupt) T2ST 0: Stop 1: Clear and start
XIN PIN
Prescaler
/4 /8 / 16 / 64 / 256 / 1024
T2IF
Figure 14-11 16-bit Timer/Counter for Timer 2, 3
14.3 8-bit Compare Output (16-bit)
The MC80F0208/16/24 has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin( T3O) as shown in Figure 14-5 . Thus, pulse out is generated by the timer match. These operation is implemented to pin, PWM3O/T3O. In this mode, the bit PWM3O/T3O of R5 Port Selection register0 (PSR0.7) should be set to "1", and the bit PWM3E of timer3 mode register (TM3) should be set to "0". This pin output the signal having a 50 : 50 duty square wave, and output frequency is same as below equation.
Oscillation Frequency f COMP = --------------------------------------------------------------------------------2 x Prescaler Value x ( TDR + 1 )
58
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
7
6 X
5
4
3
2
1
0
TM4
X
CAP4 T4CK2 T4CK1 T4CK0 T4CN T4ST BTCL 0 X X X X X
ADDRESS: 0DCH INITIAL VALUE: 00H
X means don't care T4CK[2:0]
/2
XIN PIN
Prescaler
/4 /8 / 16 / 64 / 256 / 1024 / 2048
000 001 010 011 100 101 110 111 TDR4H + TDR4L (16-bit) Higher byte Lower byte COMPARE DATA T4CN Comparator T4IF TIMER 4 INTERRUPT T4ST 0: Stop 1: Clear and start T4H + T4L (16-bit) clear
MUX
Figure 14-12 Timer 4 for only 16 bit mode
14.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 14-13. Likewise, the Timer 2 capture mode is set by bit CAP2 of timer mode register TM2 (bit CAP3 of timer mode register TM3 for Timer 3) as shown in Figure 14-14. The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when timer register T0 (T1, T2, T3) increases and matches TDR0 (TDR1, TDR2, TDR3). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 14-16, the pulse width of captured signal is wider than the timer data value (FFH) over 2 times. When external interrupt is occurred, the captured value (13H) is more little than wanted value. It can be obtained correct value by counting the number of timer overflow occurrence. Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1,T2,T3), to be captured into registers CDRx (CDR0, CDR1, CDR2, CDR3), respectively. After captured, Timer x register is cleared and restarts by hardware. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS. Refer to "19.5 External Interrupt" on page 92. In addition, the transition at INTn pin generate an interrupt. Note: The CDRn and TDRn are in same address.In the capture mode, reading operation is read the CDRn, not TDRn because path is opened to the CDRn.
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
7
6 -
5
4
3
2
1
0
TM0
-
CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST BTCL 1 X X X X X
ADDRESS: 0D0H INITIAL VALUE: --00 0000B
X means don't care 7 6 16BIT 0 T0CK[2:0] Edge Detector 5
-
4
3
2
1
0
TM1
-
CAP1 T1CK1 T1CK0 T1CN T1ST BTCL 1 X X X X
ADDRESS: 0D2H INITIAL VALUE: -0-0 0000B
-
X means don't care
EC0 PIN
/2
111 T0ST 000 001 010 011 100 101 110 MUX IEDS[1:0] CDR0 (8-bit) T0CN Capture clear 0: Stop 1: Clear and start T0 (8-bit)
XIN PIN
Prescaler
/4 /8 / 32 / 128 / 512 / 2048
"01"
INT0 PIN
"10" T1CK[1:0] "11" T1ST /1 /2 /8 11 00 01 10 MUX T1CN Capture clear T1 (8-bit)
INT0IF
INT0 INTERRUPT
0: Stop 1: Clear and start
CDR1 (8-bit) IEDS[3:2]
"01"
INT1 PIN
"10" "11"
INT1IF
INT1 INTERRUPT
Figure 14-13 8-bit Capture Mode for Timer 0, 1
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MC80F0208/16/24
7
6 -
5
4
3
2
1
0
TM2
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST BTCL 1 X X X X X
ADDRESS: 0D6H INITIAL VALUE: --00 0000B
X means don't care 7 6 5 4 3 2 1 0
TM3
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL X 0 T2CK[2:0] 0 1 X X X X
ADDRESS: 0D8H INITIAL VALUE: 00H
X means don't care
Edge Detector
EC1 PIN
/2
111 T2ST 000 001 010 011 100 101 110 MUX IEDS[5:4] CDR2 (8-bit) T2CN Capture clear 0: Stop 1: Clear and start T2 (8-bit)
XIN PIN
Prescaler
/4 /8 / 16 / 64 / 256 / 1024
"01"
INT2 PIN
"10" T3CK[1:0] "11" T3ST /1 /4 / 16 11 00 01 10 MUX T3CN Capture clear T3 (8-bit)
INT2IF
INT2 INTERRUPT
0: Stop 1: Clear and start
CDR3 (8-bit) IEDS[7:6]
"01"
INT3 PIN
"10" "11"
INT3IF
INT3 INTERRUPT
Figure 14-14 8-bit Capture Mode for Timer 2, 3
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T0
9 8 7 6 5 4 3 2 1 0
t
n n-1
This value is loaded to CDR0
~ ~
~ ~
up
-c o
un
~ ~
TIME
Ext. INT0 Pin
Interrupt Request ( INT0IF ) Interrupt Interval Period
Ext. INT0 Pin
Interrupt Request ( INT0IF )
20nS Capture ( Timer Stop )
5nS
Delay
Clear & Start
Figure 14-15 Input Capture Operation of Timer 0 Capture mode
Ext. INT0 Pin
Interrupt Request ( INT0IF ) Interrupt Interval Period=01H+FFH +01H+FFH +01H+13H=214H Interrupt Request ( T0IF ) FFH T0 13H 00H 00H FFH
Figure 14-16 Excess Timer Overflow in Capture Mode
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MC80F0208/16/24
14.5 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0]. In 16-bit mode, the bits T1CK1, T1CK0, CAP1 and 16BIT of TM1 should be set to "1" respectively as shown in Figure 14-17. The clock source of the Timer 2 is selected either internal or external clock by bit T2CK[2:0]. In 16-bit mode, the bits T3CK1,T3CK0, CAP3 and 16BIT of TM3 should be set to "1" respectively as shown in Figure 14-18. The clock source of the Timer 4 is selected either internal or external clock by bit T4CK[2:0] as shown in Figure 14-18.
7
6 -
5
4
3
2
1
0
TM0
-
CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST BTCL 1 X X X X X
ADDRESS: 0D0H INITIAL VALUE: --00 0000B
X means don't care 7 6 16BIT 1 T0CK[2:0] Edge Detector 5
-
4
3
2
1
0
TM1
-
CAP1 T1CK1 T1CK0 T1CN T1ST BTCL 1 1 1 X X
ADDRESS: 0D2H INITIAL VALUE: -0-0 0000B
-
X means don't care
EC0 PIN
/2
111 T0ST 000 001 010 011 100 101 110 MUX IEDS[1:0] T0CN Capture CDR1 + CDR0 (16-bit) Higher byte Lower byte CAPTURE DATA "01" clear 0: Stop 1: Clear and start TDR1 + TDR0 (16-bit)
XIN PIN
Prescaler
/4 /8 / 32 / 128 / 512 / 2048
INT0 PIN
"10" "11"
INT0IF
INT0 INTERRUPT
Figure 14-17 16-bit Capture Mode of Timer 0, 1
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7
6 -
5
4
3
2
1
0
TM2
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST BTCL 1 X X X X X
ADDRESS: 0D6H INITIAL VALUE: --000000B
X means don't care 7 6 5 4 3 2 1 0
TM3
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL X 1 T2CK[2:0] 0 1 1 1 X X
ADDRESS: 0D8H INITIAL VALUE: 00H
X means don't care
Edge Detector
EC1 PIN
/2
111 T2ST 000 001 010 011 100 101 110 MUX IEDS[5:4] T2CN Capture CDR3 + CDR2 (16-bit) Higher byte Lower byte CAPTURE DATA "01" clear 0: Stop 1: Clear and start TDR3 + TDR2 (16-bit)
XIN PIN
Prescaler
/4 /8 / 16 / 64 / 256 / 1024
INT2 PIN
"10" "11"
INT2IF
INT2 INTERRUPT
Figure 14-18 16-bit Capture Mode of Timer 2, 3
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MC80F0208/16/24
7
6 X
5
4
3
2
1
0
TM4
X
CAP4 T4CK2 T4CK1 T4CK0 T4CN T4ST BTCL 1 X X X X X
ADDRESS: 0DCH INITIAL VALUE: 00H
X means don't care
T4CK[2:0]
/2
XIN PIN
Prescaler
/4 /8 / 16 / 64 / 256 / 1024 / 2048
000 T4ST 001 010 011 100 101 110 111 T4CN Capture CDR4H + CDR4L (16-bit) MUX IEDS[1:0] Higher byte Lower byte CAPTURE DATA "01" 0: Stop 1: Clear and start TDR4H + TDR4L (16-bit) clear
INT3 PIN
"10" "11"
INT3IF
INT3 INTERRUPT
Figure 14-19 16-bit Capture Mode of Timer 4
Example 1: Timer0 = 16-bit timer mode, 0.5s at 4MHz LDM LDM LDM LDM SET1 EI : : Example 2: Timer0 = 16-bit event counter mode LDM LDM LDM LDM LDM SET1 EI : : PSR0,#0001_0000B;EC0 Set TM0,#0001_1111B;CounterMode TM1,#0100_1100B;16bit Mode TDR0,#<0FFH ; TDR1,#>0FFH ; T0E TM0,#0000_1111B;8uS TM1,#0100_1100B;16bit Mode TDR0,#<62499 ;8uS X 62500 TDR1,#>62499 ;=0.5s T0E
Example 3: Timer0 = 16-bit capture mode LDM LDM LDM LDM LDM LDM SET1 EI : : PSR0,#0000_0001B;INT0 set TM0,#0010_1111B;CaptureMode TM1,#0100_1100B;16bit Mode TDR0,#<0FFH ; TDR1,#>0FFH ; IEDS,#01H;Falling Edge T0E
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Preliminary
14.6 PWM Mode
The MC80F0208/16/24 has a high speed PWM (Pulse Width Modulation) functions which shared with Timer3. In PWM mode, pin R54/PWM3O outputs up to a 10-bit resolution PWM output. This pin should be configured as a PWM output by setting "1" bit PWM3O in PSR0 register. The period of the PWM3 output is determined by the T3PPR (T3 PWM Period Register) and T3PWHR[3:2] (bit3,2 of T3 PWM High Register) and the duty of the PWM output is determined by the T3PDR (T3 PWM Duty Register) and T3PWHR[1:0] (bit1,0 of T3 PWM High Register). The user writes the lower 8-bit period value to the T3PPR and the higher 2-bit period value to the T3PWHR[3:2]. And writes duty value to the T3PDR and the T3PWHR[1:0] same way. The T3PDR is configured as a double buffering for glitchless PWM output. In Figure 14-20, the duty data is transferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) PWM3 Period = [PWM3HR[3:2]T3PPR] X Source Clock PWM3 Duty = [PWM3HR[1:0]T3PDR] X Source Clock LDM LDM LDM LDM LDM TM3,#1010_1000b ; Set Clock & PWM3E T3PPR,#199 ; Period :800uS=4uSX(199+1) T3PDR,#99 ; Duty:400uS=4uSX(99+1) PWM3HR,00H TM3,#1010_1011b ; Start timer3 The bit POL of TM3 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to "00H", the PWM output is determined by the bit POL (1: Low, 0: High). It can be changed duty value when the PWM output. However the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 14-22. As it were, the absolute duty time is not changed in varying frequency. But the changed period value must greater than the duty value. Note: If changing the Timer3 to PWM function, it should be stop the timer clock firstly, and then set period and duty register value. If user writes register values while timer is in operation, these register could be set with certain values. Ex) Sample Program @4MHz 4uS
The relation of frequency and resolution is in inverse proportion. Table 14-4 shows the relation of PWM frequency vs. resolution. If it needed more higher frequency of PWM, it should be reduced resolution. Frequency Resolution 10-bit 9-bit 8-bit 7-bit T3CK[1:0] = 00(250nS) 3.9kHz 7.8kHz 15.6kHz 31.2kHz T3CK[1:0] = 01(1uS) 1.95kHz 3.90kHz 7.81kHz 15.6kHz T3CK[1:0] = 10(4uS) 0.97kHz 1.95kHz 3.90kHz 7.8kHz
Table 14-4 PWM Frequency vs. Resolution at 4MHz
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MC80F0208/16/24
R/W 7
R/W 6
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0
TM3
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL X 0 1 0 X X X X
ADDRESS: 0D8H INITIAL VALUE: 00H X:The value "0" or "1" corresponding your operation.
7
6 -
5
-
4 -
W 3
W 2
W 1
W 0
T3PWHR
-
T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0 BTCL
ADDRESS: 0DBH INITIAL VALUE: ---- 0000B Bit Manipulation Not Available X:The value "0" or "1" corresponding your operation.
-
X
X
X
X
Period High
Duty High
W 7
W 6
W 5
W 4
W 3 BTCL
W 2
W 1
W 0
T3PPR
ADDRESS: 0D9H INITIAL VALUE: 0FFH
R/W 7
R/W 6
R/W 5
R/W 4
R/W 3 BTCL
R/W 2
R/W 1
R/W 0
T3PDR
X 0 1 0
ADDRESS: 0DAH INITIAL VALUE: 00H
X
X
X
X
T3PWHR[1:0] PWM3O [PSR0.7] SQ
Clear
T2 clock source [T2CK]
T3CK[1:0]
T3ST 0 : Stop 1 : Clear and Start
T3PPR(8-bit)
11 Prescaler /1 /4 / 16 00 01 10 MUX T3CN
Comparator
R 2-bit
T3(8-bit)
XIN PIN
R53/PWM3O/T3O PIN
POL
Comparator
Slave
T3PDR(8-bit)
T3PWHR[1:0]
Master
T3PDR(8-bit)
Figure 14-20 PWM3 Mode
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~ ~
~ ~
Source clock T3 PWM3E T3ST T3CN PWM3O [POL=1] PWM3O [POL=0]
00 01 02 03 04
~~ ~~
Duty Cycle [ (1+7Fh) x 250nS = 32uS ] Period Cycle [ (3FFh+1) x 250nS = 256uS, 3.9KHz ]
T3CK[1:0] = 00 ( XIN ) T3PWHR = 0CH T3PPR = FFH T3PDR = 7FH
~ ~
Period
T3PWHR3 1
T3PWHR2 1 T3PWHR0 0
T3PPR (8-bit) FFH T3PDR (8-bit) 7FH
Duty
T3PWHR1 0
Figure 14-21 Example of PWM at 4MHz
T3CK[1:0] = 10 ( 2us ) PWM3HR = 00H T3PPR = 0DH T3PDR = 04H Source clock T3 PWM3O POL=1 Duty Cycle [ (04h+1) x 2uS = 10uS ] Period Cycle [ (1+0Dh) x 2uS = 28uS, 35.5KHz ] Duty Cycle [ (04h+1) x 2uS = 10uS ] Duty Cycle [ (04h+1) x 2uS = 10uS ]
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04
Write T3PPR to 09H
Period Cycle [ (1+09h) x 2uS = 20uS, 50KHz ]
Figure 14-22 Example of Changing the Period in Absolute Duty Cycle (@8MHz)
68
~ ~
~~~ ~~~ ~ ~ ~ ~ ~ ~
7E
7F
80
3FF
00
01
02
~ ~
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MC80F0208/16/24
15. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 10-bit digital value. The A/ D module has sixteen analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog supply voltage is connected to AVDD of Sample & Hold logic of A/D module. The AVDD was separated with VDD in order to minimize the degradation of operation characteristic by power supply noise. The A/D module has three registers which are the control register ADCM and A/D result register ADCRH and ADCRL. The ADCRH[7:6] is used as ADC clock source selection bits too. The register ADCM, shown in Figure 15-4, controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O. It is selected for the corresponding channel to be converted by setting ADS[3:0]. The A/D port is set to analog input port by ADEN and ADS[3:0] regardless of port I/O direction register. The port unselected by ADS[3:0] operates as normal port. ADCRH and ADCRL contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCRH and ADCRL, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag ADCIF is set. See Figure 15-1 for operation flow. The block diagram of the A/D module is shown in Figure 15-3. The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes 7 times of conversion source clock. The period of actual A/D conversion clock should be minimally 1s
Analog Input 0~1000pF User Selectable
AN0~AN7
Figure 15-2 Analog Input Pin Connecting Capacitor
Enable A/D Converter
A/D Converter Cautions
A/D Input Channel Select
(1) Input range of AN0 to AN7 The input voltage of AN0 to AN7 should be within the specification range. In particular, if a voltage above AVDD or below AVSS is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. The conversion values of the other channels may also be affected. (2) Noise countermeasures In order to maintain 10-bit resolution, attention must be paid to noise on pins AVDD and AN0 to AN7. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended in some cases that a capacitor be connected externally as shown in Figure 15-2 in order to reduce noise. The capacitance is user-selectable and appropriately determined according to the target system.
NO
Conversion Source Clock Select
A/D Start (ADST = 1)
NOP
ADSF = 1 YES Read ADCR
(3) Pins AN0/R60 to AN7/R67 The analog input pins AN0 to AN7 also function as input/output port (PORT R6) pins. When A/D conversion is performed with any of pins AN0 to AN15 selected, be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion.
Figure 15-1 A/D Converter Operation Flow
How to Use A/D Converter
The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register
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(4) AVDD pin input impedance A series resistor string of approximately 5K is connected between the AVDD pin and the AVSS pin. Therefore, if the output impedance of the analog power source is high, this will result in
parallel connection to the series resistor string between the AVDD pin and the AVSS pin, and there will be a large analog supply voltage error.
ADEN
AVDD AVSS
Resistor Ladder Circuit
8-bit ADC
R60/AN0 R61/AN1
Successive MUX Sample & Hold Approximation Circuit ADCIF ADC INTERRUPT
R66/AN6 R67/AN7
ADC8 0 1
10-bit Mode ADS[4:2] 98 ADCR (10-bit) 10-bit ADCR 00 ADCRH 10 ADC Result Register ADCRL (8-bit) ADCRH 10 98
8-bit Mode
32
10-bit ADCR
ADCRL (8-bit)
ADC Result Register
Figure 15-3 A/D Block Diagram
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R/W 7
R/W 6
5 -
ADCM
ADEN ADCK
R/W R/W R/W R 3 2 1 0 ADS2 BTCL ADS0 ADST ADSF ADS1
R/W 4
ADDRESS: 0EFH INITIAL VALUE: 00-0 0001B A/D status bit 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion. After one cycle, bit is cleared to "0" by hardware. Analog input channel select 000: Channel 0 (AN0) 100: Channel 4 (AN4) 001: Channel 1 (AN1) 101: Channel 5 (AN5) 010: Channel 2 (AN2) 110: Channel 6 (AN6) 011: Channel 3 (AN3) 111: Channel 7 (AN7) A/D converter Clock Source Devide Ratio Selection bit 0: Clock Source fPS / 4 1: Clock Source fPS / 8 A/D converter Enable bit 0: A/D converter module turn off and current is not flow. 1: Enable A/D converter
W 7
W 6
W 5
R 4 3 BTCL 2 1
R 0 ADDRESS: 0F0H INITIAL VALUE: 010- ----B A/D Conversion High Data ADC 8-bit Mode select bit 0: 10-bit Mode 1: 8-bit Mode A/D Conversion Clock (fPS) Source Selection 00: fXIN 01: fXIN / 2 10: fXIN / 4 11: fXIN / 8 ADDRESS: 0F1H INITIAL VALUE: Undefined
ADCRH
PSSEL1 PSSEL0 ADC8
R 7
R 6
R 5
R 4
ADCRL
R 3 BTCL
R 2
R 1
R 0
A/D Conversion Low Data
ADCK 0 0 0 0 1 1 1 1
PSSEL1 0 0 1 1 0 0 1 1
PSSEL0 0 1 0 1 0 1 0 1
PS Clock Selection PS = fXIN / 4 PS = fXIN / 8 PS = fXIN / 16 PS = fXIN / 32 PS = fXIN / 8 PS = fXIN / 16 PS = fXIN / 32 PS = fXIN / 64 PS : Conversion Clock
Figure 15-4 A/D Converter Control & Result Register
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16. SERIAL INPUT/OUTPUT (SIO)
The serial Input/Output is used to transmit/receive 8-bit data serially. The Serial Input/Output(SIO) module is a serial interface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. This SIO is 8bit clock synchronous type and consists of serial I/O data register, serial I/O mode register, clock selection circuit, octal counter and control circuit as illustrated in Figure 16-1. The SO pin is designed to input and output. So the Serial I/O(SIO) can be operated with minimum two pin. Pin R42/SCK, R43/SI, and R44/SO pins are controlled by the Serial Mode Register. The contents of the Serial I/O data register can be written into or read out by software. The data in the Serial Data Register can be shifted synchronously with the transfer clock signal.
SIOST SCK[1:0] /4 / 16 POL 00 01 10 11 "0" Clock "1" Start
SIOSF clear
XIN PIN
Timer0 Overflow
Prescaler
Complete
overflow
SIO CONTROL CIRCUIT
Clock
Octal Counter (3-bit)
SIOIF Serial communication Interrupt
SCK PIN
"11" not "11" SCK[1:0]
MUX
IOSW SM0 SOUT
SO PIN
IOSW 1 Input shift register
SI PIN
0 Shift SIOR
Internal Bus
Figure 16-1 SIO Block Diagram
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MC80F0208/16/24
Serial I/O Mode Register(SIOM) controls serial I/O function. According to SCK1 and SCK0, the internal clock or external clock can be selected.
Serial I/O Data Register(SIOR) is an 8-bit shift register. First LSB is send or is received.
R/W 7
R/W 6
R/W 5
SIOM
POL IOSW SM1
R/W R/W R/W R 3 2 1 0 SM0 BTCL SCK0 SIOST SIOSF SCK1
R/W 4
ADDRESS: 0E2H INITIAL VALUE: 0000 0001B Serial transmission status bit 0: Serial transmission is in progress 1: Serial transmission is completed Serial transmission start bit Setting this bit starts an Serial transmission. After one cycle, bit is cleared to "0" by hardware. Serial transmission Clock selection 00: fXIN / 4 01: fXIN / 16 10: TMR0OV(Timer0 Overflow) 11: External Clock Serial transmission Operation Mode 00: Normal Port(R42,R43,R44) 01: Sending Mode(SCK,R43,SO) 10: Receiving Mode(SCK,SI,R44) 11: Sending & Receiving Mode(SCK,SI,SO) Serial Input Pin Selection bit 0: SI Pin Selection 1: SO Pin Selection
Serial Clock Polarity Selection bit 0: Data Transmission at Falling Edge Received Data Latch at Rising Edge 1: Data Transmission at Rising Edge Received Data Latch at Falling Edge
SIOR
R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BTCL
ADDRESS: 0E3H INITIAL VALUE: Undefined
Sending Data at Sending Mode Receiving Data at Receiving Mode
Figure 16-2 SIO Control Register
16.1 Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 of SIOM) to "1". After one cycle of SCK, SIOST is cleared automatically to "0". At the default state of POL bit clear, the serial output data from 8-bit shift register is output at falling edge of SCLK, and input data is latched at rising edge of SCLK pin (Refer to Figure 163). When transmission clock is counted 8 times, serial I/O counter is cleared as `0". Transmission clock is halted in "H" state and serial I/O interrupt(SIOIF) occurred.
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SIOST
SCK [R42] (POL=0)
SO [P44] SI [R43] (IOSW=0) IOSWIN [P44] (IOSW=1) SIOSF (SIO Status) SIOIF (SIO Int. Req)
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Figure 16-3 Serial I/O Timing Diagram at POL=0
SIOST SCK [R42] (POL=1)
SO [R44] SI [R43] (IOSW=0) IOSWIN [R44] (IOSW=1) SIOSF (SIO Status) SIOIF (SIO Int. Req)
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Figure 16-4 Serial I/O Timing Diagram at POL=1
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16.2 The method of Serial I/O
1. Select transmission/receiving mode. 2. In case of sending mode, write data to be send to SIOR. 3. Set SIOST to "1" to start serial transmission. 4. The SIO interrupt is generated at the completion of SIO and SIOIF is set to "1". In SIO interrupt service routine, correct transmission should be tested. 5. In case of receiving mode, the received data is acquired by reading the SIOR.
LDM LDM NOP LDM SIOR,#0AAh SIOM,#0011_1100b SIOM,#0011_1110b ;set tx data ;set SIO mode ;SIO Start
Note: When external clock is used, the frequency should be less than 1MHz and recommended duty is 50%. If both transmission mode is selected and transmission is performed simultaneously, error will be made.
16.3 The Method to Test Correct Transmission
Serial I/O Interrupt Service Routine 0
SIOSF 1 SIOE = 0
Abnormal
Write SIOM
SIOIF 1 Normal Operation
0
Overrun Error
- SIOE: Interrupt Enable Register High IENH(Bit3) - SIOIF: Interrupt Request Flag Register High IRQH(Bit3)
Figure 16-5 Serial IO Method to Test Transmission
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17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
17.1 UART Serial Interface Functions
The Universal Asynchronous Receiver/Transmitter(UART) enables full-duplex operation wherein one byte of data after the start bit is transmitted and received. The on-chip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rates. In addition, a baud rate can also be defined by dividing clocks input to the ACLK pin. The UART driver consists of RXR, TXR, ASIMR, ASISR and BRGCR register. Clock asynchronous serial I/O mode (UART) can be selected by ASIMR register. Figure 17-1 shows a block diagram of the UART driver. Note: The UART1 control register ASIMR1,ASISR1, BRGCR1, RXR1 and TXR1 are located at EE6H ~ EE9H address. These address must be accessed(read and written) by absolute addressing manipulation instruction.
Internal Data Bus
Receive Buffer Register (RXR)
RxE
RxD PIN
Receive Shift Register (RX)
Transmit Shift Register (TXR)
2 TxE PE
1 FE
0 OVE (ASISR)
TxD PIN
Transmit Controller (Parity Addition)
TXxIOF
Receive Controller (Parity Check)
RXxIOF
UARTxIF (UARTx interrupt)
ACLK PIN
fXIN/2 ~ fXIN/27
Baud Rate Generator
Figure 17-1 UART Block Diagram
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RECEIVE RxE
ACLK PIN
MUX fXIN/2 ~ fXIN/27 match 1/2 (Divider) Tx_Clock 5-bit counter
Decoder match
-
TPS2
TPS1 TPS0
MDL3 MDL2
MDL1 MDL0 (BRGCR) 5-bit counter
1/2 (Divider)
Rx_Clock
TxE Internal Data Bus SEND
Figure 17-2 Baud Rate Generator Block Diagram
R/W
R/W
R/W
R/W
R/W
WTIOF
R/W
WDTIOF
IFR
MSB
-
-
RX0IOF TX0IOF
RX1IOF TX1IOF
ADDRESS: 0DFH INITIAL VALUE: --00 0000B WDT interrupt occurred flagNOTE1 WT interrupt occurred flagNOTE1 UART1 Tx interrupt occurred flagNOTE2 UART1 Rx interrupt occurred flagNOTE2 UART0 Tx interrupt occurred flagNOTE3 UART0 Rx interrupt occurred flagNOTE3
LSB
NOTE1 : In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. NOTE2 : In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. NOTE3 : In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register.
Figure 17-3 IFR : Interrupt Flag Register
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17.2 Serial Interface Configuration
The UART interface consists of the following hardware. Item Register Configuration Transmit shift register (TXR) Receive buffer register (RXR) Receive shift register Serial interface mode register (ASIMR) Serial interface status register (ASISR) Baudrate generator control register (BRGCR) receive shift register (RXSR). When the data length is set as 7 bits, receive data is sent to bits 0 to 6 of RXR0. In this case, the MSB of RXR always becomes 0. RXR can be read by an 8 bit memory manipulation instruction. It cannot be written. The RESET input sets RXR0 to 00H. Note: The same address is assigned to RXR and the transmit shift register (TXR). During a write operation, values are written to TXR.
Control register
Table 17-1 Serial Interface Configuration
Receive shift register
This register converts serial data input via the RxD pin to paralleled data. When one byte of data is received at this register cannot be manipulated directly by a program.
Transmit shift register (TXR)
This is the register for setting transmit data. Data written to TXR0 is transmitted as serial data. When the data length is set as 7 bit, bit 0 to 6 of the data written to TX0 are transferred as transmit data. Writing data to TXR0 starts the transmit operation. TXR0 can be written by an 8 bit memory manipulation instruction. It cannot be read. The RESET input sets TXR0 to 0FFH. Note: Do not write to TXR during a transmit operation. The same address is assigned to TXR and the receive buffer register (RXR). A read operation reads values from RXR.
Asynchronous serial interface mode register (ASIMR)
This is an 8 bit register that controls UART serial transfer operation. ASIMR is set by a 1 bit or 8 bit memory manipulation intruction. The RESET input sets ASIMR to 0000_-00-B. Table 174 shows the format of ASIMR. Note: Do not switch the operation mode until the current serial transmit/receive operation has stopped. .
Receive buffer register (RXR)
This register is used to hold receive data. When one byte of data is received, one byte of new receive data is transferred from the
R/W 7
R/W 6
R/W 5
ASIMR0
TXE0 RXE0 PS01
R/W R/W R/W 3 2 1 PS00 BTCL SL0 ISRM0 -
R/W 4
0 -
ADDRESS: 0E6H INITIAL VALUE: 0000 -00-B
UART0 Receive interrupt request is issued when an error occurs bit 0: Receive Completion Interrupt Control When Error occurs 1: Receive completion interrupt request is not issued when an error occur UART0 Stop Bit Length for Specification for Transmit Data bit 0: 1 bit 1: 2 bit UART0 Parity Bit Specification bit 00: No parity 01: Zero parity always added during transmission. No parity detection during reception (parity errors do not occur) 10: Odd parity 11: Even parity UART0 Tx/Rx Enable bit 00: Not used UART0 (R46, R47) 01: UART0 Receive only Mode(RxD, R47) 10: UART0 Transmit only Mode(R46, TxD) 11: UART0 Receive & Transmit Mode(RxD, TxD)
Figure 17-4 Asynchronous Serial Interface Mode register (ASIMR0) Format
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Asynchronous serial interface status register0 (ASISR)
When a receive error occurs during UART mode, this register indicates the type of error. ASISR can be read by an 8 bit memory manipulation instruction. The RESET input sets ASISR0 to ----000B. Figure 17-5 shows the format of ASISR. .
7
6 -
5 -
4 -
ASISR0
-
3 BTCL -
R 2 PE0
R 1
R 0
FE0 OVE0
ADDRESS: 0E7H INITIAL VALUE: ---- -000B
UART0 Parity Error Flag 0: No parity error 1: Parity error (Transmit data parity not matched) UART0 Frame Error Flag 0: No Frame error 1: Framing errorNote1 (stop bit not detected) UART0 Overrun Error Flag 0: No overrun error 1: Overrun errorNote2 (Next receive operation was completed before data was read from receive buffer register (RXR))
Note 1. Even if a stop bit length is set to 2 bits by setting bit2(SL) in ASIMR, stop bit detection during a recive operation only applies to a stop bit length of 1bit. 2. Be sure to read the contents of the receive buffer register(RXR) when an overrun error has occurred. Until the contents of RXR are read, futher overrun errors will occur when receiving data.
Figure 17-5 Asynchronous Serial Interface Status Register (ASISR) Format
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Baud rate generator control register (BRGCR)
This register sets the serial clock for serial interface. BRGCR is set by an 8 bit memory manipulation instruction. The RESET input sets BRGCR to -001_0000B. Figure 17-6 shows the format of BRGCR. .
7
BRGCR0
-
R R R 3 2 1 0 BTCL TPS02 TPS01 TPS00 MDL03MDL02MDL01MDL00 6 5 4
ADDRESS: 0E8H INITIAL VALUE: -001 0000B
UART0 Input Clock Selection 0000: fSCK / 16 0001: fSCK / 17 0010: fSCK / 18 0011: fSCK / 19 0100: fSCK / 20 0101: fSCK / 21 0110: fSCK / 22 0111: fSCK / 23 1000: fSCK / 24 1001: fSCK / 25 1010: fSCK / 26 1011: fSCK / 27 1100: fSCK / 28 1101: fSCK / 29 1110: fSCK / 30 1111: Setting prohibited UART0 Source Clock Selection for 5 bit count 000: ACLK/R45 001: fXIN / 2 010: fXIN / 4 011: fXIN / 8 100: fXIN / 16 101: fXIN / 32 110: fXIN / 64 111: fXIN / 128
Caution Writing to BRGCR0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. Therefore, do not write to BRGCR0 during a communication operation.
Remarks 1. fSCK : Source clock for 5 bit counter 2. n : Value set via TPS0 to TPS2 ( 0 n 7 ) 3. k : Source clock for 5 bit counter ( 0 k 14 )
Figure 17-6 Baud Rate Generator Control Register0(BRGCR) Format
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17.3 Communication operation
The transmit operation is enabled when bit 7 (TXE0) of the asynchronous serial interface mode register (ASIMR) is set to 1. The transmit operation is started when transmit data is written to the transmit shift register (TXR). The timing of the transmit completion interrupt request is shown in Figure 17-8. The receive operation is enabled when bit 6 (RXE0) of the asynchronous serial interface mode register (ASIMR) is set to 1, and input via the RxD pin is sampled. The serial clock specified by ASIMR is used to sample the RxD pin. Once reception of one data frame is completed, a receive completion interrupt request (INT_RX0) occurs. Even if an error has occurred, the receive data in which the error occurred is still transferred to RXR. When ASIMR bit 1 (ISRM0) is cleared to 0 upon occurrence of an error, and INT_RX0 occurs. When ISRM bit is set to 1, INT_RX0 does not occur in case of error occurrence. Figure 17-8 shows the timing of the asynchronous serial interface receive completion interrupt request. In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. Each processing step is determined by IFR as shown in Figure 177.
UART0(UART1) Interrupt Request
Tx0IOF(Tx1IOF) =1 Tx0(Tx1) Interrupt Routine
=0
Clear Tx0IOF(Tx1IOF)
Rx0IOF(Rx1IOF) =1 Rx0(Rx1) Interrupt Routine
=0
Clear Rx0IOF(Rx1IOF)
RETI
Figure 17-7 Shared Interrupt Vector of UART
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1. Stop bit Length : 1 bit
1 data frame TxD RxD
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
character bits TX INTERRUPT RX INTERRUPT
2. Stop bit Length : 2 bit
1 data frame TxD RxD
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
character bits TX INTERRUPT RX INTERRUPT
3. Stop bit Length : 1 bit, No parity
1 data frame TxD RxD
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
character bits TX INTERRUPT RX INTERRUPT
1 data frame consists of following bits. - Start bit : 1 bit - Character bits : 8 bits - Parity bit : Even parity, Odd parity, Zero parity, No parity - Stop bit(s) : 1 bit or 2 bits
Figure 17-8 UART data format and interrupt timing diagram
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17.4 Relationship between main clock and baud rate
The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. Transmit/Receive clock generation for baud rate is made by using main system clock which is divided. The baud rate generated from the main system clock is determined according to the following formula.
fXIN=11.0592M Baud Rate (bps) 600 1200 2400 4800 9600 19200 31250 38400 57600 76800 115200 BRGCR 72H 62H 52H 42H 36H 32H 28H 22H 18H ERR (%) 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 0.00
fXIN=10.0M BRGCR 70H 60H 50H 40H 34H 30H 26H 20H 16H ERR (%) 1.73 1.73 1.73 1.73 0.00 1.73 1.35 1.73 1.36
fXIN=8.0M BRGCR 7AH 6AH 5AH 4AH 3AH 30H 2AH 21H 1AH 11H ERR (%) 0.16 0.16 0.16 0.16 0.16 0.00 0.16 2.11 0.16 2.12
fXIN=6.0M BRGCR 74H 64H 54H 44H 34H 28H 24H 1AH 14H ERR (%) 2.34 2.34 2.34 2.34 2.34 0.00 2.34 0.16 2.34 -
fXIN=4.0M BRGCR 7AH 6AH 5AH 4AH 3AH 2AH 20H 1AH 11H ERR (%) 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 2.12 -
fXIN=2.0M BRGCR 6AH 5AH 4AH 3AH 2AH 1AH 10H ERR (%) 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -
Baud Rate = fXIN / ( 2n+1(k+16) )
Remarks 1. fXIN : Main system clock oscillation frequency
When ACLK is selected as the source clock of the 5-bit counter, substitute the input clock frequency to ACLK pin for in the above expression.
2. fSCK : Source clock for 5 bit counter 3. n : Value set via TPS00 to TPS02 ( 0 n 7 ) 4. k : Source clock for 5 bit counter ( 0 k 14 )
Figure 17-9 Relationship between main clock and Baud Rate
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18. BUZZER FUNCTION
The buzzer driver block consists of 6-bit binary counter, buzzer register BUZR, and clock source selector. It generates squarewave which has very wide range frequency (488Hz ~ 250kHz at fXIN= 4MHz) by user software. A 50% duty pulse can be output to R13/BUZO pin to use for piezo-electric buzzer drive. Pin R13 is assigned for output port of Buzzer driver by setting the bit 2 of PSR1(address 0F9H) to "1". For PSR1 register, refer to Figure 18-2. Example: 5kHz output at 4MHz. LDM LDM
X means don't care
The bit 0 to 5 of BUZR determines output frequency for buzzer driving. Equation of frequency calculation is shown below.
f XIN f BUZ = --------------------------------------------------------------------------2 x DivideRatio x ( BUR + 1 )
fBUZ: Buzzer frequency fXIN: Oscillator frequency Divide Ratio: Prescaler divide ratio by BUCK[1:0] BUR: Lower 6-bit value of BUZR. Buzzer period value.
BUZR,#0011_0001B PSR1,#XXXX_X1XXB
The frequency of output signal is controlled by the buzzer control register BUZR. The bit 0 to bit 5 of BUZR determine output frequency for buzzer driving.
R13 port data /8 Prescaler / 16 / 32 / 64 6-BIT BINARY COUNTER
00 01 10 11 MUX 2
MUX 0 F/F 1
XIN PIN
R13/BUZO PIN
Comparator Compare data BUZO 6 BUR [0E0H] Internal bus line PSR1 [0F9H] Port selection register 1
Figure 18-1 Block Diagram of Buzzer Driver
ADDRESS: 0E0H RESET VALUE: 0FFH W W W W W W W W
ADDRESS: 0F9H RESET VALUE: ---- -0--B
BUZR
BUCK1 BUCK0
PSR1
-
-
-
-
-
BUZO
-
-
BUR[5:0] Buzzer Period Data Source clock select 00: fXIN / 8 01: fXIN / 16 10: fXIN / 32 11: fXIN / 64
R13/BUZO Selection 0: R13 port (Turn off buzzer) 1: BUZO port (Turn on buzzer)
Figure 18-2 Buzzer Register & PSR1
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The 6-bit counter is cleared and starts the counting by writing signal at BUZR register. It is incremental from 00H until it matches 6-bit BUR value.
When main-frequency is 4MHz, buzzer frequency is shown as below Table 18-1.
BUR [5:0] 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
BUR[7:6] 00 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 01 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 10 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 11 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977
BUR [5:0] 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
BUR[7:6] 00 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.907 01 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 10 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 11 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488
Table 18-1 buzzer frequency (kHz unit)
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19. INTERRUPTS
The MC80F0208/16/24 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit, and Master enable flag ("I" flag of PSW). Fifteen interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 19-1 and interrupt priority is shown in Table 19-1. The External Interrupts INT0 ~ INT3 each can be transition-activated (1-to-0 or 0-to-1 transition) by selection IEDS register. The flags that actually generate these interrupts are bit INT0IF, INT1IF, INT2IF and INT3IF in register IRQH. When an external interrupt is generated, the generated flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The Timer 0 ~ Timer 4 Interrupts are generated by T0IF, T1IF, T2IF, T3IF and T4IF which is set by a match in their respective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register. The AD converter Interrupt is generated by ADCIF which is set by finishing the analog to digital conversion. The Watchdog timer and Watch Timer Interrupt is generated by WDTIF and WTIF which is set by a match in Watchdog timer register or Watch timer register. The IFR(Interrupt Flag Register) is used for discrimination of the interrupt source among these two Watchdog timer and Watch Timer Interrupt.
Internal bus line [0EAH] IENH IRQH [0ECH] INT0 INT1 INT2 INT3 UART0 Tx/Rx UART1 Tx/Rx Serial Communication Timer 0 IRQL [0EDH] Timer 1 Timer 2 Timer 3 Timer 3 A/D Converter Watchdog Timer Watch Timer BIT T1IF T2IF T3IF T4IF ADCIF WDTIF WTIF BITIF INT0IF INT1IF INT2IF INT3IF Priority Control UART0IF UART1IF SIOIF T0IF To CPU I-flag Interrupt Master Enable Flag Interrupt Vector Address Generator Release STOP/SLEEP Interrupt Enable Register (Higher byte) I-flag is in PSW, it is cleared by "DI", set by "EI" instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware.
[0EBH]
IENL
Interrupt Enable Register (Lower byte)
Internal bus line
Figure 19-1 Block Diagram of Interrupt
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The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflow in the timer counter register. The UART0 receive/transmit interrupt is generated by UART0IF is set by completion of UART0 data reception or transmission. The IFR(Interrupt Flag Register) is used for discrimination of the interrupt source among these two UART0 receive and UART0 transmit Interrupt. The SIO interrupt is generated by SIOIF which is set by completion of SIO data reception or transmission. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW on Figure 8-3), the interrupt enable register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except Power-on reset and software BRK interrupt. The Table 19-1 shows the Interrupt priority. Vector addresses are shown in Figure 8-6. Interrupt enable registers are shown in Figure 19-2. These registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. Reset/Interrupt Hardware Reset External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 UART0 Rx/Tx Interrupt UART1 Rx/Tx Interrupt Serial Input/Output Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 Timer/Counter 4 ADC Interrupt Watchdog/Watch Timer Basic Interval Timer Symbol RESET INT0 INT1 INT2 INT3 UART0 UART1 SIO Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 ADC WDT_WT BIT Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Table 19-1 Interrupt Priority
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W T0E LSB
IENH
INT0E
INT1E INT2E INT3E UART0E UART1E SIOE
ADDRESS: 0EAH INITIAL VALUE: 0000 0000B Timer/Counter 0 interrupt enable flag Serial Communication interrupt enable flag UART1 Tx/Rx interrupt enable flag UART0 Tx/Rx interrupt enable flag External interrupt 0 enable flag External interrupt 1 enable flag External interrupt 2 enable flag External interrupt 3 enable flag
MSB
R/W
R/W T2E
R/W T3E
R/W
R/W
R/W
R/W
R/W BITE LSB
IENL
T1E MSB
T4E ADCE WDTE WTE
ADDRESS: 0EBH INITIAL VALUE: 0000 0000B Basic Interval Timer interrupt enable flag Watch timer interrupt enable flag Watchdog timer interrupt enable flag A/D Converter interrupt enable flag Timer/Counter 4 interrupt enable flag Timer/Counter 3 interrupt enable flag Timer/Counter 2 interrupt enable flag Timer/Counter 1 interrupt enable flag
Figure 19-2 Interrupt Enable Flag Register
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R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W T0IF LSB
IRQH
INT0IF INT1IF INT2IF INT3IF UART0IF UART1IF SIOIF
ADDRESS: 0ECH INITIAL VALUE: 0000 0000B Timer/Counter 0 interrupt request flag Serial Communication interrupt request flag UART1Tx/Rx interrupt request flag UART0 Tx/Rx interrupt request flag External interrupt 3 request flag External interrupt 2 request flag External interrupt 1 request flag External interrupt 0 request flag
MSB
R/W
R/W T2IF
R/W T3IF
R/W
R/W
R/W
R/W
R/W LSB
IRQL
T1IF MSB
T4IF ADCIF WDTIF WTIF BITIF
ADDRESS: 0EDH INITIAL VALUE: 0000 0000B Basic Interval Timer interrupt request flag Watch timer interrupt request flag Watchdog timer interrupt request flag A/D Converter interrupt request flag Timer/Counter 4 interrupt request flag Timer/Counter 3 interrupt request flag Timer/Counter 2 interrupt request flag Timer/Counter 1 interrupt request flag
R/W
R/W
R/W
R/W
R/W
R/W LSB
IFR
MSB
-
-
RX0IOF TX0IOF RX1IOF TX1IOF WTIOF WDTIOF
ADDRESS: 0DFH INITIAL VALUE: --00 0000B WDT interrupt occurred flagNOTE1 WT interrupt occurred flagNOTE1 UART1 Tx interrupt occurred flagNOTE2 UART1 Rx interrupt occurred flagNOTE2 UART0 Tx interrupt occurred flagNOTE3 UART0 Rx interrupt occurred flagNOTE3
NOTE1 : In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. NOTE2 : In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. NOTE3 : In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register.
Figure 19-3 Interrupt Request Flag Register & Interrupt Flag Register
19.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 cycles of fXIN (2s at fXIN =4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI].
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19.1.1 Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed.
System clock
Instruction Fetch Address Bus
PC SP SP-1 SP-2 V.L. V.H. New PC
Data Bus Internal Read Internal Write
Not used
PCH
PCL
PSW
V.L.
ADL
ADH
OP code
Interrupt Processing Step V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.
Interrupt Service Task
Figure 19-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Basic Interval Timer Vector Table Address
Entry Address
A interrupt request is not accepted until the I-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced. When nested interrupt service is required, the I-flag should be set to "1" by "EI" instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
0FFE0H 0FFE1H
012H 0E3H
0E312H 0E313H
0EH 2EH
Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program.
19.1.2 Saving/Restoring General-purpose Register
During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the general-purpose registers. Example: Register save using push and pop instructions INTxx: PUSH PUSH PUSH A X Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG.
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interrupt processing
POP POP POP RETI
Y X A
;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN
main task acceptance of interrupt interrupt service task saving registers
General-purpose register save/restore using push and pop instructions;
interrupt return
restoring registers
19.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 19-5.
B-FLAG BRK or TCALL0 =1 BRK INTERRUPT ROUTINE RETI
=0
TCALL0 ROUTINE
RET
Figure 19-5 Execution of BRK/TCALL0
19.3 Shared Interrupt Vector
In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. Each
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processing step is determined by IFR as shown in Figure 19-6.
UART0(UART1) Interrupt Request
WDT or WT Interrupt Request
Tx0IOF(Tx1IOF) =1
=0
WDTIF =1 WDT Interrupt Routine
=0
WTIF =1 WDT Interrupt Routine
=0
Tx0(Tx1) Interrupt Routine
Clear Tx0IOF(Tx1IOF)
Clear WDTIF
Clear WTIF
Rx0IOF(Rx1IOF) =1 Rx0(Rx1) Interrupt Routine
=0
RETI Clear Rx0IOF(Rx1IOF)
RETI
Figure 19-6 Software Flowchart of Shared Interrupt Vector
19.4 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing
Main Program service TIMER 1 service INT0 service
through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.
enable INT0 disable other EI
Occur TIMER1 interrupt
Occur INT0
In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.
enable INT0 enable other
Figure 19-7 Execution of Multi Interrupt
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Example: During Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER1: PUSH PUSH PUSH LDM LDM EI : : A X Y IENH,#80H IENL,#0
: : : : LDM LDM POP POP POP RETI
;Enable INT0 only ;Disable other int. ;Enable Interrupt
IENH,#0FFH ;Enable all interrupts IENL,#0FFH Y X A
19.5 External Interrupt
The external interrupt on INT0, INT1, INT2 and INT3 pins are edge triggered depending on the edge selection register IEDS (address 0EEH) as shown in Figure 19-8. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge.
01
INT0 pin
10 11
INT0IF
INT0 INTERRUPT
01
INT1 pin
10 11
INT1IF
INT1 INTERRUPT
01
INT2 pin
10 11
INT2IF
INT2 INTERRUPT
01
INT3 pin
10 11 2 2 IEDS [0EEH] 2 2
INT3IF
INT3 INTERRUPT
Edge selection Register
Figure 19-8 External Interrupt Block Diagram INT0 ~ INT3 are multiplexed with general I/O ports (R10, R11, R12, R50). To use as an external interrupt pin, the bit of port selection register PSR0 should be set to "1" correspondingly. Example: To use as an INT0 and INT2 : ;**** Set external interrupt port as pull-up state. LDM PU1,#0000_0101B ; ;**** Set port as an external interrupt port LDM PSR0,#0000_0101B ; ;**** Set Falling-edge Detection LDM IEDS,#0001_0001B :
Response Time
The INT0 ~ INT3 edge are latched into INT0IF ~ INT3IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 19-9 shows interrupt response timings.
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max. 12 fXIN
8 fXIN
Interrupt Interrupt goes latched active
Interrupt processing
Interrupt routine
Figure 19-9 Interrupt Response Timing Diagram
MSB W
W
W
W
W
W
W
LSB W ADDRESS: 0EEH INITIAL VALUE: 00H
IEDS
IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L BTCL INT3 INT2 INT1 INT0
Edge selection register 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling)
W
W
-
W EC1E
W
W
W
W
W ADDRESS: 0F8H INITIAL VALUE: 0-00 0000B
PSR0
PWM3O
EC0E BTCL INT2E INT1E INT0E INT3E
MSB 0: R54 1: PWM3O/T3O
LSB 0: R10 1: INT0 0: R11 1: INT1
0: R51 1: EC1 0: R15 1: EC0
0: R12 1: INT2 0: R50 1: INT3
Figure 19-10 IEDS register and Port Selection Register PSR0
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20. OPERATION MODE
The system clock controller starts or stops the main-frequency clock oscillator. The operating mode is generally divided into the main active mode. Figure 20-1 shows the operating mode transition diagram. System clock control is performed by the system clock mode register, SCMR. During reset, this register is initialized to "0" so that the main-clock operating mode is selected.
SLEEP Mode
In this mode, the CPU clock stops while peripherals and the oscillation source continues to operate normally.
STOP Mode
In this mode, the system operations are all stopped, holding the internal states valid immediately before the stop at the low power consumption level. The main oscillation source stops, but the sub clock oscillation and watch timer by sub clock and RC-oscillated watchdog timer don't stop.
Main Active Mode
This mode is fast-frequency operating mode. The CPU and the peripheral hardware are operated on the high-frequency clock. At reset release, this mode is invoked.
* Note1 : Stop released by Reset, Watch Timer, Watchdog Timer Timer(event counter), External interrupt, SIO (External clock), UART0, UART1 * Note3 * Note2 : Sleep released by Reset, or All interrupts
Main Active Mode
* Note1 / * Note2 Main : Oscillation Sub : Oscillation or stop System Clock : Main
Stop / Sleep Mode
Main : Oscillation or Stop Sub : Oscillation System Clock : Stop
* Note3 : 1) Stop mode Admission LDM SSCR, #5AH STOP NOP NOP 2) Sleep mode Admission LDM SSCR, #0FH
Figure 20-1 Operating Mode
20.1 Operation Mode Switching
In the Main active mode, only the high-frequency clock oscillator is used. In the Sub active mode, the low-frequency clock oscillation is used, so the low power voltage operation or the low power consumption operation can be enabled. Instruction execution does not stop during the change of operation mode. In this case, some peripheral hardware capabilities may be affected. For details, refer to the description of the relevant operation. The following describes the switching between the Main active mode and the Sub active mode. During reset, the system clock mode register is initialized at the Main active mode. It must be set to the Sub active mode for reducing the power consumption.
Shifting from the Normal operation to the SLEEP mode
If the CPU clock stops and the SLEEP mode is invoked, the CPU stops while other peripherals are operate normally. The ways of release from this mode are by setting the RESET pin to low and all available interrupts. For more detail, See "21. POWER SAVING OPERATION" on page 95.
Shifting from the Normal operation to the STOP mode
If the main-frequency clock oscillation stops and the STOP mode is invoked, the CPU stops and other peripherals are stop too. But sub-frequency clock oscillation operate continuously if enabled previously. After the STOP operation is released by reset, the operation mode is changed to Main active mode. The methods of release from this mode are Reset, Watch Timer, Timer/Event counter, SIO(External clock), UART, and External Interrupt. For more details, see "21. POWER SAVING OPERATION" on page 95. Note: In the STOP and SLEEP operating modes, the power consumption by the oscillator and the internal hardware is reduced. However, the power for the pin interface (depending on external circuitry and program) is not directly associated with the low-power consumption operation. This must be considered in system design as well as interface circuit design.
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21. POWER SAVING OPERATION
The MC80F0208/16/24 has two power-down modes. In powerdown mode, power consumption is reduced considerably. For applications where power consumption is a critical factor, device provides two kinds of power saving functions, STOP mode and SLEEP mode. Table 21-1 shows the status of each Power Saving Mode. SLEEP mode is entered by the SSCR register to "0Fh"., and STOP mode is entered by STOP instruction after the SSCR register to "5Ah".
21.1 Sleep Mode
In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operate normally but CPU stops. Movement of all peripherals is shown in Table 21-1. SLEEP mode is entered by setting the SSCR register to "0Fh". It is released by Reset or interrupt. To be released by interrupt, interrupt should be enabled before SLEEP mode.
W 7
W 6
W 5
W 4
W 3
W 2
W 1
W 0 ADDRESS: 0F5H INITIAL VALUE: 0000 0000B Power Down Control 5AH: STOP mode 0FH: SLEEP mode
SSCR
NOTE :
To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution. At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released. To get into SLEEP mode, SSCR must be set to 0FH.
Figure 21-1 STOP and SLEEP Control Register
Release the SLEEP mode
The exit from SLEEP mode is hardware reset or all interrupts. Reset re-defines all the Control registers but does not change the on-chip RAM. Interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction following the SLEEP instruction. It will not vector to interrupt service routine. (refer to Figure 21-4)
When exit from SLEEP mode by reset, enough oscillation stabilization time is required to normal operation. Figure 21-3 shows the timing diagram. When released from the SLEEP mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before SLEEP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By interrupts, exit from SLEEP mode is shown in Figure 21-2. By reset, exit from SLEEP mode is shown in Figure 21-3.
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.
Oscillator (XIN pin)
~~ ~~
~~ ~~
Internal Clock
~ ~
~~ ~~
External Interrupt
~ ~
SLEEP Instruction Executed Normal Operation SLEEP Operation
Normal Operation
Figure 21-2 SLEEP Mode Release Timing by External Interrupt
~ ~
Oscillator (XIN pin) CPU Clock RESET Internal RESET
SLEEP Instruction Execution Normal Operation
SLEEP Operation
Figure 21-3 Timing of SLEEP Mode Release by Reset
~ ~ ~ ~ ~ ~ ~ ~
Stabilization Time tST = 65.5mS @4MHz Normal Operation
~ ~ ~ ~
21.2 Stop Mode
In the Stop mode, the main oscillator, system clock and peripheral clock is stopped, but the sub clock oscillation and Watch Timer by sub clock and RC-oscillated watchdog timer continue to operate. With the clock frozen, all functions are stopped, but the onchip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up.
"STOP" which starts the STOP operating mode.
Note: The Stop mode is activated by execution of STOP instruction after setting the SSCR to "5AH". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated.
* The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held. * The program counter stop the address of the instruction to be executed after the instruction
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The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. Note: After STOP instruction, at least two or more NOP instruction should be written. Ex) LDM CKCTLR,#0FH ;more than 20ms LDM SSCR,#5AH STOP NOP ;for stabilization time NOP ;for stabilization time In the STOP operation, the dissipation of the power associated Peripheral CPU RAM Basic Interval Timer Watchdog Timer Watch Timer Timer/Counter Buzzer, ADC SIO UART Oscillator Sub Oscillator I/O Ports Control Registers Internal Circuit Prescaler Address Data Bus STOP Mode Stop Retain Halted
with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means.
SLEEP Mode Stop Retain Operates Continuously Stop Stop Operates Continuously Stop Only operate with external clock Only operate with external clock Oscillation Oscillation Retain Retain Sleep mode Active Retain
Stop (Only operates in RC-WDT mode) Stop Halted(Only when the event counter mode is enabled, timer operates normally) Stop Only operate with external clock Only operate with external clock Stop(XIN=L, XOUT=H) Oscillation Retain Retain Stop mode Retain Retain Reset, Timer(EC0,1), SIO, UART0(using ACLK0), UART1(using ACLK1) Watch Timer( RC-WDT mode), Watchdog Timer( RC-WDT mode), External Interrupt
Release Source
Reset, All Interrupts
Table 21-1 Peripheral Operation During Power Saving Mode
Release the STOP mode
The source for exit from STOP mode is hardware reset, external interrupt, Timer(EC0,1), Watch Timer, WDT, SIO or UART. Reset re-defines all the Control registers but does not change the onchip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag =
0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine. (refer to Figure 21-4) When exit from Stop mode by external interrupt, enough oscillation stabilization time is required to normal operation. Figure 215 shows the timing diagram. When released from the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal op-
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eration. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized.
By reset, exit from Stop mode is shown in Figure 21-6.
STOP INSTRUCTION STOP Mode
Interrupt Request =0
Corresponding Interrupt Enable Bit (IENH, IENL)
IENH or IENL ? =1 STOP Mode Release
Master Interrupt Enable Bit PSW[2]
I-FLAG =1
=0
Interrupt Service Routine
Next INSTRUCTION
Figure 21-4 STOP Releasing Flow by Interrupts .
Oscillator (XIN pin)
~~ ~~
~ ~ ~ ~
Internal Clock
~ ~
~ ~
External Interrupt
~ ~
STOP Instruction Executed
~~ ~~
~~ ~~
BIT Counter
n
n+1 n+2
n+3
0 Clear
1
FE
FF
0
1
2
Normal Operation
Stop Operation
Stabilization Time tST > 20ms by software
Normal Operation
Before executing Stop instruction, Basic Interval Timer must be set properly by software to get stabilization time which is longer than 20ms.
Figure 21-5 STOP Mode Release Timing by External Interrupt
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STOP Mode
~ ~
Oscillator (XI pin) Internal Clock RESET Internal RESET
~ ~
STOP Instruction Execution Time can not be control by software
Figure 21-6 Timing of STOP Mode Release by Reset
21.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode
In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after setting the bit RCWDT of CKCTLR to "1". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) (at RC-watchdog timer mode). Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watchdog timer interrupt service routine(Figure 8-6). However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal Reset signal and execute the reset processing(Figure 21-8). If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.(refer to Figure 21-4) When exit from Stop mode at Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required to normal operation. Figure 21-7 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from internal RC-Oscillated Watchdog Timer mode is shown in Figure 21-8.
Note: Caution: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM WDTR,#1111_1111B LDM CKCTLR,#0010_1110B LDM SSCR,#0101_1010B STOP NOP ;for stabilization time NOP ;for stabilization time
The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt or watchdog timer interrupt
~~ ~~ ~ ~ ~ ~
Stabilization Time tST = 65.5mS @4MHz
~~ ~~ ~ ~
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~ ~
Oscillator (XIN pin) Internal RC Clock
~ ~
~ ~ ~ ~
Internal Clock External Interrupt ( or WDT Interrupt )
~ ~
STOP Instruction Execution
~ ~
Clear Basic Interval Timer
~ ~ ~ ~
BIT Counter
N-2
N-1
N
N+1
N+2
00
01
FE
FF
00
00
~ ~
Normal Operation
STOP mode at RC-WDT Mode
Stabilization Time tST > 20mS
Normal Operation
Figure 21-7 Stop Mode Release at Internal RC-WDT Mode by External Interrupt or WDT Interrupt
RCWDT Mode
~ ~
Oscillator (XIN pin) Internal RC Clock
~ ~
~ ~ ~ ~
Internal Clock RESET RESET by WDT Internal RESET
~ ~
STOP Instruction Execution Time can not be control by software
Figure 21-8 Internal RC-WDT Mode Releasing by Reset
~ ~ ~ ~
Stabilization Time tST = 65.5mS @4MHz
~ ~ ~ ~
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21.4 Minimizing Current Consumption
The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turnoff output drivers that are sourcing or sinking current, if it is practical.
VDD INPUT PIN internal pull-up OPEN INPUT PIN VDD VDD i=0
VDD
O
O
i GND VDD
i
Very weak current flows
X
Weak pull-up current flows
X
OPEN
i=0
GND
O
O
When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption.
Figure 21-9 Application Example of Unused Input Port
OUTPUT PIN ON OPEN ON OFF i GND VDD ON OFF OFF
OUTPUT PIN VDD L ON OFF i GND ON i=0 GND L VDD
O
OFF
X
X O
O
In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port .
In the left case, much current flows from port to GND.
Figure 21-10 Application Example of Unused Output Port than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means. It should be set properly in order that current flow through port doesn't exist. First consider the port setting to input mode. Be sure that there is
Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher
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no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if uncertain voltage level (not VSS or VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow.
If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. The port setting to High or Low is decided by considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pulldown register, it is set to low.
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22. OSCILLATOR CIRCUIT
The MC80F0208/16/24 have oscillation circuits internally. XIN and XOUT are input and output for frequency. Respectively, inverting amplifier which can be configured for being used as an on-chip oscillator, as shown in Figure 22-1.
C1 XOUT C2
8MHz
XIN VSS External Clock
Open
XOUT
XIN
Recommended Crystal Oscillator Ceramic Resonator C1,C2 = 20pF 10pF C1,C2 = 20pF 10pF
External Oscillator
Crystal or Ceramic Oscillator
Figure 22-1 Oscillation Circuit Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. In addition, see Figure 22-2 for the layout of the crystal.
XOUT
Note: Minimize the wiring length. Do not allow the wiring to intersect with other signal conductors. Do not allow the wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground it to any ground pattern where high current is present. Do not fetch signals from the oscillator.
XIN
Figure 22-2 Layout of Oscillator PCB circuit
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23. RESET
The MC80F0208/16/24 have four types of reset generation procedures; they are an external reset input, a watch-dog timer reset, On-chip Hardware Program counter RAM page register G-flag Operation mode (PC) (RPR) (G) Initial Value (FFFFH) - (FFFEH) 0 0 Main-frequency clock power fail processor reset, and address fail reset. Table 23-1 shows on-chip hardware initialization by reset action. On-chip Hardware Peripheral clock Watchdog timer Control registers Power fail detector Initial Value Off Disable Refer to Table 8-1 on page 27 Disable
Table 23-1 Initializing Internal Status by Reset Action
External Reset Input
The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. After reset, 65.5ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 23-2. Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before read or tested it. When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. A connection for simple power-on-reset is shown in Figure 23-1.
1 2 3 4 5 6 7 VCC
10k 7036P
+
to the RESET pin 10uF
Figure 23-1 Simple Power-on-Reset Circuit
~ ~
Oscillator (XIN pin) RESET
~ ~ ~ ~
ADDRESS BUS DATA BUS
?
?
?
?
FFFE FFFF Start
~~ ~~
?
?
?
?
FE
ADL
ADH
OP
Stabilization Time tST =65.5mS at 4MHz
Figure 23-2 Timing Diagram after Reset
~ ~
Reset Process Step 1 fXIN /1024 MAIN PROGRAM tST = x 256
Address Fail Reset
The Address Fail Reset is the function to reset the system by checking code access of abnormal and unwished address caused by erroneous program code itself or external noise, which could
not be returned to normal operation and would become malfunction state. If the CPU tries to fetch the instruction from ineffective code area or RAM area, the address fail reset is occurred. Please refer to Figure 11-2 for setting address fail option.
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24. POWER FAIL PROCESSOR
The MC80F0208/16/24 has an on-chip power fail detection circuitry to immunize against power noise. A configuration register, PFDR, can enable or disable the power fail detect circuitry. Whenever VDD falls close to or below power fail voltage for 100ns, the power fail situation may reset or freeze MCU according to PFDM bit of PFDR. Refer to "Figure 24-1 Power Fail Voltage Detector Register" on page 105. In the in-circuit emulator, power fail function is not implemented and user can not experiment with it. Therefore, after final development of user program, this function may be experimented or evaluated. Note: User can select power fail voltage level according to PFS0, PFS1 bit of CONFIG register(703FH) at the FLASH (MC80F0208/16/24) but must select the power fail voltage level to define PFD option of "Mask Order & Verification Sheet" at the mask chip(MC80C0208/16/24), because the power fail voltage level of mask chip (MC80C0208/16/24) is determined according to mask option. Note: If power fail voltage is selected to 2.4V or 2.7V on below 3V operation, MCU is freezed at all the times.
Power Fail Function Enable/Disable Level Selection
FLASH PFDEN flag PFS0 bit PFS1 bit
MASK PFDEN flag Mask option
Table 24-1 Power fail processor
PFDR
7 -
6 -
5 -
4 -
3 -
R/W 2
R/W 1
R/W 0 ADDRESS: 0F7H INITIAL VALUE: ---- -000B Power Fail Status 0: Normal operate 1: Set to "1" if power fail is detected PFD Operation Mode 0 : MCU will be frozen by power fail detection 1 : MCU will be reset by power fail detection PFD Enable Bit 0: Power fail detection disable 1: Power fail detection enable
PFDEN PFDM PFDS
* Cautions :
Be sure to set bits 3 through 7 to "0".
Figure 24-1 Power Fail Voltage Detector Register
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RESET VECTOR
PFDS =1 NO RAM Clear Initialize RAM Data
YES
PFDS = 0 Skip the initial routine
Initialize All Ports Initialize Registers
Function Execution
Figure 24-2 Example S/W of Reset flow by Power fail
VDD Internal RESET VDD When PFDM = 1 Internal RESET VDD Internal RESET 65.5mS t < 65.5mS 65.5mS 65.5mS
VPFDMAX VPFDMIN
VPFDMAX VPFDMIN
VPFDMAX VPFDMIN
Figure 24-3 Power Fail Processor Situations (at 4MHz operation)
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25. FLASH PROGRAMMING
The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as security bit. This area is not accessible during normal execution but is readable and writable during FLASH program / verify mode. The Device Configuration Area register is located at the address 20FFH.
CONFIG
7 -
6 -
5 -
4 -
3 -
2 1 0 PFS1 PFS0 LOCK
ADDRESS: 20FFH INITIAL VALUE: 00H Code Protect (Available FLASH version) 0 : Lock Disable 1 : Lock Enable (main cell read protection) PFD Level Selection 00: PFD = 2.7V 01: PFD = 2.7V 10: PFD = 3.0V 11: PFD = 2.4V
Figure 25-1 Device Configuration Area
25.1 Lock bit
The lock bit exists in Device Configuration Area register. If lock bit is programmed and user tries to read FLASH memory cell, the output data from the data port is 5AH that means the normal protection operation of user program data.Once the lock bit is programmed, the user can't modify and read the data of user program area.
25.2 Power Fail Detector
The power fail detection provides 3 level of detection, 2.4V, 2.7V and 3.0V. The default level of detection is 2.7V and this level is applied if user does not select the specific level in FLASH programming S/W tools. For more information, Refer to "24. POWER FAIL PROCESSOR" on page 105.
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J_USERB
VDD AVDD GND R67 R65 R63 R61 GND R57 R55 R53 R51 GND R47 R45 R43 R41 GND R37 R35 R33 R31 GND U_Reset GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
J_USERA
26. Emulator EVA. Board Setting
VCC AVDD GND R66 R64 R62 R60 GND R56 R54 R52 R50 GND R46 R44 R42 R40 GND R36 R34 R32 R30 GND U_XOUT GND
VDD R70 R72 R74 R76 GND R80 R82 R84 R86 GND R00 R02 R04 R06 GND R10 R12 R14 R16 GND R20 R22 R24 R26
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
VDD R71 R73 R75 R77 GND R81 R83 R85 R87 GND R01 R03 R05 R07 GND R11 R13 R15 R17 GND R21 R23 R25 R27

Preliminary
MC80F0208/16/24

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MC80F0208/16/24
DIP Switch and VR Setting
Before execute the user program, keep in your mind the below configuration DIP S/W Description This connector is only used for a device over 32 PIN. This connector is only used for a device under 32 PIN. ON/OFF Setting For the MC80F0208/16/24. For the MC80F0204. Must be ON position. 1
ON

Eva. select switch
ON : For the MC80F0208/16/24. OFF : For the MC80F0204.
ON
OFF ON
Use User's AVDD
These switches select the AVDD source. ON & OFF : Use Eva. VDD OFF & ON : Use User AVDD
2 3
OFF
Use Eva. VDD
SW2 4
AVDD pin select switch Normally OFF. EVA. chip can be reset by external user target board. ON : Reset is available by either user target system board or Emulator RESET switch. OFF : Reset the MCU by Emulator RESET switch. Does not work from user target board. Normally OFF. MCU XOUT pin is disconnected internally in the Emulator. Some circumstance user may connect this circuit. ON : Output XOUT signal OFF : Disconnect circuit
This switch select the /Reset source.
5
This switch select the Xout signal on/off.
This switch select Eva. B/D Power supply source.
MDS MDS
SW3 1
USER Use MDS Power USER Use User's Power
Normally MDS. This switch select Eva. B/D Power supply source.
SW4
1 2
This switch select the R22 or SXOUT. This switch select the R21 or SXIN.
These switchs select the Normal I/O port(off) or Sub-Clock (on). It is reserved for the MC80F0448. ON : SXOUT, SXIN OFF : R22, R21 Don't care (MC80F0208/16/24).
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Preliminary
DIP S/W
Description 1 2 3 4 5 6 These switches select the R33 or XIN These switches select the R34 or XOUT These switches select the R35 or /Reset This is External oscillation socket(CAN Type. OSC)
ON/OFF Setting This switch select the Normal I/O port(on&off) or special function select(off&on). It is reserved for the MC80F0204. ON & OFF : R33,R34,R35 Port selected. OFF & ON : XOUT, XIN , /Reset selected. Don't care (MC80F0208/16/24). This is for External Clock(CAN Type. OSC).
SW5
-
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Preliminary
MC80F0208/16/24
27. IN-SYSTEM PROGRAMMING (ISP)
27.1 Getting Started / Installation
The following section details the procedure for accomplishing the installation procedure.
3. Turn your target B/D power switch ON. Your target B/ D must be configured to enter the ISP mode. 4. Run the MagnaChip ISP software. 5. Press the Reset Button in the ISP S/W. If the status windows shows a message as "Connected", all the conditions for ISP are provided.
1. Connect the serial(RS-232C) cable between a target board and the COM port of your PC. 2. Configure the COM port of your PC as following.
Baudrate Data bit Parity Stop bit Flow control 115,200 8 No 1 No
27.2 Basic ISP S/W Information
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Preliminary
Function Load HEX File Save HEX File Erase Blank Check Program Read Verify Option Write Option AUTO Auto Option Write Edit Buffer Fill Buffer Goto OSC. ______ MHz Start ______ End ______ Checksum Com Port Baud Rate Select Device Page Up Key Page Down Key
Description Load the data from the selected file storage into the memory buffer. Save the current data in your memory buffer to a disk storage by using the Intel Motorolla HEX format. Erase the data in your target MCU before programming it. Verify whether or not a device is in an erased or unprogrammed state. This button enables you to place new data from the memory buffer into the target device. Read the data in the target MCU into the buffer for examination. The checksum will be displayed on the checksum box. Assures that data in the device matches data in the memory buffer. If your device is secured, a verification error is detected. Progam the configuration data of target MCU. The security locking is performed with this button. Set the configuration data of target MCU. The security locking is set with this button. Erase & Program & Verify. If selected with check mark, the option write is performed after erasure and write. Modify the data in the selected address in your buffer memory Fill the selected area with a data. Display the selected page. Enter your target system's oscillator value with discarding below point. Starting address End address Display the checksum(Hexdecimal) after reading the target device. Select serial port. Select UART baud rate. Select target device. Display the previous page of your memory buffer. Display the higher page than the current location. Table 1. ISP Function Description
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MC80F0208/16/24
27.3 Hardware Conditions to Enter the ISP Mode
The In-System Programming (ISP) is performed without removing the microcontroller from the target system. The In-System Programming(ISP) facility consists of a series of internal hardware resources coupled with internal firmware through the serial port. The In-System Programming (ISP) facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The boot loader can be executed by holding ALEB high, RST/VPP as +9V, and ACLK0 with the OSC. 1.8432MHz. The ISP function uses five pins: TxD0, RxD0, ALEB, ACLK0 and RST/VPP.
VDD(+5V) VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
MC80F0208K/16K/24K
R47 / TxD0 R46 / RxD0 R45 / ACLK0
Tx_Data Rx_Data 1.8432MHz
+9V X-TAL 2MHz~12MHz
RST/VPP RESET XIN XOUT
R30 ALEB VSS
VDD
ISP Configuration
Figure 27-1 ISP Configuration Note: Considerations to implement ISP function in a user target board
* The ACLK0 must be connected to the specifed oscillator. * Connect the +9V to RST/Vpp pin directly. * The ALEB pin must be pulled high. * The main clk must be higher than 2MHz.
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Preliminary
27.4 Reference ISP Circuit diagram
The ISP S/W and H/W circuit diagram are provided at www.magnachipmcu.com . To get a ISP B/D, contact to sales department. The following circuit diagram is for reference use.
2N2907 CON1 Female DB9
1 6 2 7 3 8 4 9 5 1k VDD(+5V) MAX232 14 T1OUT 7 T2OUT 13 R1IN 8 R2IN 2 V+ 16 VCC 6 V15 GND
100 VDD(+5V) 10uF/35V
RxD TxD DTR GND VSS VSS + 1uF + 1uF
T1IN 11 T2IN 10 12 R1OUT R2OUT 9 1 C1+ + 1uF 3 C14 C2+ + 1uF 5 C2-
8.2k
10k
+
J2
RESET/VPP VDD VSS ACLK_CLK MCU_TxD MCU_RxD 1 2 3 4 5 6
From PC
VSS 22 22 100pF
VSS
100pF
VSS
VDD(+5V)
VDD(+5V)
VSS
VSS
10uF/16V
J3
VDD VSS +
22
0.1uF
X1 Vcc Out Gnd OSC 1.8432MHz
22
* VDD : +4.5 ~ +5.5V * VPP : VDD + 4V
VSS
0.1uF
VSS
VSS
External VDD
The ragne of VDD must be from 5.5V to 4.5 and the minimum operation frequency is 2MHz. If the user supplied VDD is out of range, the external power is needed instead of the target system VDD. For the ISP operation, power consumption required is less than 30mA.
Figure 27-2 Reference ISP Circuit Diagram
Figure 27-3 MagnaChip supplied ISP Board
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To MCU
APPENDIX
GMS800 Series
A. INSTRUCTION
A.1 Terminology List
Terminology A X Y PSW #imm dp !abs [] {} { }+ .bit A.bit dp.bit M.bit rel upage n + x Accumulator X - register Y - register Program Status Word 8-bit Immediate data Direct Page Offset Address Absolute Address Indirect expression Register Indirect expression Register Indirect expression, after that, Register auto-increment Bit Position Bit Position of Accumulator Bit Position of Direct Page Memory Bit Position of Memory Data (000H~0FFFH) Relative Addressing Data U-page (0FF00H~0FFFFH) Offset Address Table CALL Number (0~15) Addition
0 Bit Position
Description
Upper Nibble Expression in Opcode
y - x / ()
1 Bit Position
Upper Nibble Expression in Opcode
Subtraction Multiplication Division Contents Expression AND OR Exclusive OR NOT Assignment / Transfer / Shift Left Shift Right Exchange Equal Not Equal
~ =
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GMS800 Series
A.2 Instruction Map
LOW 00000 HIGH
00 -
00001 01 SET1 dp.bit
00010 02
00011 03
00100 04 ADC #imm SBC #imm CMP #imm OR #imm AND #imm EOR #imm LDA #imm LDM dp,#imm
00101 05 ADC dp SBC dp CMP dp OR dp AND dp EOR dp LDA dp STA dp
00110 06 ADC dp+X SBC dp+X CMP dp+X OR dp+X AND dp+X EOR dp+X LDA dp+X STA dp+X
00111 07 ADC !abs SBC !abs CMP !abs OR !abs AND !abs EOR !abs LDA !abs STA !abs
01000 08 ASL A ROL A LSR A ROR A INC A DEC A TXA
01001 09 ASL dp ROL dp LSR dp ROR dp INC dp DEC dp LDY dp STY dp
01010 0A
01011 0B
01100 0C BIT dp COM dp TST dp CMPX dp CMPY dp DBNE dp LDX dp STX dp
01101 0D POP A POP X POP Y POP PSW CBNE dp+X XMA dp+X LDX dp+Y STX dp+Y
01110 0E PUSH A PUSH X PUSH Y PUSH PSW TXSP
01111 0F BRK BRA rel PCALL Upage RET INC X DEC X DAS
000
BBS BBS A.bit,rel dp.bit,rel
TCALL SETA1 0 .bit TCALL CLRA1 2 .bit TCALL 4 TCALL 6 NOT1 M.bit OR1 OR1B
001
CLRC
010
CLRG
011
DI
100
CLRV
TCALL AND1 8 AND1B TCALL EOR1 10 EOR1B TCALL 12 TCALL 14 LDC LDCB STC M.bit
101
SETC
TSPX
110
SETG
XCN
111
EI
TAX
XAX
STOP
LOW 10000 HIGH
10 BPL rel BVC rel BCC rel BNE rel BMI rel BVS rel BCS rel BEQ rel
10001 11 CLR1
dp.bit
10010 12 BBC
A.bit,rel
10011 13 BBC
dp.bit,rel
10100 14 ADC {X} SBC {X} CMP {X} OR {X} AND {X} EOR {X} LDA {X} STA {X}
10101 15 ADC !abs+Y SBC !abs+Y CMP !abs+Y OR !abs+Y AND !abs+Y EOR !abs+Y LDA !abs+Y STA !abs+Y
10110 16 ADC [dp+X] SBC [dp+X] CMP [dp+X] OR [dp+X] AND [dp+X] EOR [dp+X] LDA [dp+X] STA [dp+X]
10111 17 ADC [dp]+Y SBC [dp]+Y CMP [dp]+Y OR [dp]+Y AND [dp]+Y EOR [dp]+Y LDA [dp]+Y STA [dp]+Y
11000 18 ASL !abs ROL !abs LSR !abs ROR !abs INC !abs DEC !abs LDY !abs STY !abs
11001 19 ASL dp+X ROL dp+X LSR dp+X ROR dp+X INC dp+X DEC dp+X LDY dp+X STY dp+X
11010 1A TCALL 1 TCALL 3 TCALL 5 TCALL 7 TCALL 9 TCALL 11 TCALL 13 TCALL 15
11011 1B JMP !abs CALL !abs MUL DBNE Y DIV XMA {X} LDA {X}+ STA {X}+
11100 1C BIT !abs TEST !abs
11101 1D ADDW dp SUBW dp
11110 1E LDX #imm LDY #imm CMPX #imm CMPY #imm INC Y DEC Y XAY
11111 1F JMP [!abs] JMP [dp] CALL [dp] RETI
000
001
010
TCLR1 CMPW !abs dp CMPX !abs CMPY !abs XMA dp LDX !abs STX !abs LDYA dp INCW dp DECW dp STYA dp CBNE dp
011
100
TAY
101
TYA
110
DAA
111
XYX
NOP
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GMS800 Series
A.3 Instruction Set
Arithmetic / Logic Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Mnemonic
ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs + Y ADC [ dp + X ] ADC [ dp ] + Y ADC { X } AND #imm AND dp AND dp + X AND !abs AND !abs + Y AND [ dp + X ] AND [ dp ] + Y AND { X } ASL A ASL dp ASL dp + X ASL !abs CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [ dp + X ] CMP [ dp ] + Y CMP { X } CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y
Op Code
04 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 44 45 46 47 55 56 57 54 5E 6C 7C 7E 8C 9C 2C DF CF A8 A9 B9 B8 AF BE
Byte No
2 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 2 2 3 3 2 2 1 2 2 3 2 2 3 2 1 1 1 2 2 3 1 1
Cycle No
2 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 2 3 4 4 5 6 6 3 2 3 4 2 3 4 4 3 3 2 4 5 5 2 2 Arithmetic shift left
C
Operation
Add with carry. A(A)+(M)+C
Flag
NVGBHIZC
NV--H-ZC
Logical AND A (A)(M) N-----Z-
76543210
N-----ZC
"0"
Compare accumulator contents with memory contents (A) -(M)
N-----ZC
Compare X contents with memory contents (X)-(M) Compare Y contents with memory contents (Y)-(M) 1'S Complement : ( dp ) ~( dp ) Decimal adjust for addition Decimal adjust for subtraction Decrement M (M)-1 N-----ZC N-----ZN-----ZC N-----ZC N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZN-----ZC
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GMS800 Series
No.
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 DIV
Mnemonic
Op Code
9B A4 A5 A6 A7 B5 B6 B7 B4 88 89 99 98 8F 9E 48 49 59 58 5B 64 65 66 67 75 76 77 74 28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34 4C CE
Byte No
1 2 2 2 3 3 2 2 1 1 2 2 3 1 1 1 2 2 3 1 2 2 2 3 3 2 2 1 1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1 2 1
Cycle No
12 2 3 4 4 5 6 6 3 2 4 5 5 2 2 2 4 5 5 9 2 3 4 4 5 6 6 3 2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3 3 5 Subtract with Carry Logical shift right Increment M (M)+1 Exclusive OR A (A)(M)
Operation
Divide : YA / X Q: A, R: Y
Flag
NVGBHIZC NV--H-Z-
EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X ] EOR [ dp ] + Y EOR { X } INC A INC dp INC dp + X INC !abs INC X INC Y LSR A LSR dp LSR dp + X LSR !abs MUL OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [ dp + X ] OR [ dp ] + Y OR { X } ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [ dp + X ] SBC [ dp ] + Y SBC { X } TST dp XCN
N-----Z-
N-----ZC N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZC
76543210 C "0"
Multiply : YA Y x A Logical OR A (A)(M)
N-----Z-
N-----Z-
Rotate left through Carry
C 76543210
N-----ZC
Rotate right through Carry
76543210 C
N-----ZC
A ( A ) - ( M ) - ~( C ) NV--HZC
Test memory contents for negative or zero, ( dp ) - 00H Exchange nibbles within the accumulator A7~A4 A3~A0
N-----ZN-----Z-
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MAR. 2005
GMS800 Series
Register / Memory Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Mnemonic
LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [ dp + X ] LDA [ dp ] + Y LDA { X } LDA { X }+ LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + X LDY !abs STA dp STA dp + X STA !abs STA !abs + Y STA [ dp + X ] STA [ dp ] + Y STA { X } STA { X }+ STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs TAX TAY TSPX TXA TXSP TYA XAX XAY XMA dp XMA dp+X XMA {X} XYX
Op Code
C4 C5 C6 C7 D5 D6 D7 D4 DB E4 1E CC CD DC 3E C9 D9 D8 E5 E6 E7 F5 F6 F7 F4 FB EC ED FC E9 F9 F8 E8 9F AE C8 8E BF EE DE BC AD BB FE
Byte No
2 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 2 2 3 3 2 2 1 1 2 2 3 2 2 3 1 1 1 1 1 1 1 1 2 2 1 1
Cycle No
2 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 4 5 5 6 7 7 4 4 4 5 5 4 5 5 2 2 2 2 2 2 4 4 5 6 5 4 Load Y-register Y(M) Load accumulator A(M)
Operation
Flag
NVGBHIZC
N-----Z-
X- register auto-increment : A ( M ) , X X + 1 Load memory with immediate data : ( M ) imm Load X-register X (M) N-----Z--------
N-----Z-
Store accumulator contents in memory (M)A --------
X- register auto-increment : ( M ) A, X X + 1 Store X-register contents in memory (M) X Store Y-register contents in memory (M) Y Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Transfer stack-pointer contents to X-register : X sp Transfer X-register contents to accumulator: A X Transfer X-register contents to stack-pointer: sp X Transfer Y-register contents to accumulator: A Y Exchange X-register contents with accumulator :X A Exchange Y-register contents with accumulator :Y A Exchange memory contents with accumulator (M)A Exchange X-register contents with Y-register : X Y N-----Z--------------N-----ZN-----ZN-----ZN-----ZN-----ZN-----Z----------------------
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GMS800 Series
16-BIT operation
No.
1 2 3 4 5 6 7
Mnemonic
ADDW dp CMPW dp DECW dp INCW dp LDYA dp STYA dp SUBW dp
Op Code
1D 5D BD 9D 7D DD 3D
Byte No
2 2 2 2 2 2 2
Cycle No
5 4 6 6 5 5 5
Operation
16-Bits add without Carry YA ( YA ) + ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : (YA) - (dp+1)(dp) Decrement memory pair ( dp+1)( dp) ( dp+1) ( dp) - 1 Increment memory pair ( dp+1) ( dp) ( dp+1) ( dp ) + 1 Load YA YA ( dp +1 ) ( dp ) Store YA ( dp +1 ) ( dp ) YA 16-Bits subtract without carry YA ( YA ) - ( dp +1) ( dp)
Flag
NVGBHIZC NV--H-ZC N-----ZC N-----ZN-----ZN-----Z-------NV--H-ZC
Bit Manipulation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mnemonic
AND1 M.bit AND1B M.bit BIT dp BIT !abs CLR1 dp.bit CLRA1 A.bit CLRC CLRG CLRV EOR1 M.bit EOR1B M.bit LDC M.bit LDCB M.bit NOT1 M.bit OR1 M.bit OR1B M.bit SET1 dp.bit SETA1 A.bit SETC SETG STC M.bit TCLR1 !abs TSET1 !abs
Op Code
8B 8B 0C 1C y1 2B 20 40 80 AB AB CB CB 4B 6B 6B x1 0B A0 C0 EB 5C 3C
Byte No
3 3 2 3 2 2 1 1 1 3 3 3 3 3 3 3 2 2 1 1 3 3 3
Cycle No
4 4 4 5 4 2 2 2 2 5 5 4 4 5 5 5 4 2 2 2 6 6 6
Operation
Bit AND C-flag : C ( C ) ( M .bit ) Bit AND C-flag and NOT : C ( C ) ~( M .bit ) Bit test A with memory : Z ( A ) ( M ) , N ( M 7 ) , V ( M6 ) Clear bit : ( M.bit ) "0" Clear A bit : ( A.bit ) "0" Clear C-flag : C "0" Clear G-flag : G "0" Clear V-flag : V "0" Bit exclusive-OR C-flag : C ( C ) ( M .bit ) Bit exclusive-OR C-flag and NOT : C ( C ) ~(M .bit) Load C-flag : C ( M .bit ) Load C-flag with NOT : C ~( M .bit ) Bit complement : ( M .bit ) ~( M .bit ) Bit OR C-flag : C ( C ) ( M .bit ) Bit OR C-flag and NOT : C ( C ) ~( M .bit ) Set bit : ( M.bit ) "1" Set A bit : ( A.bit ) "1" Set C-flag : C "1" Set G-flag : G "1" Store C-flag : ( M .bit ) C Test and clear bits with A : A - ( M ) , ( M ) ( M ) ~( A ) Test and set bits with A : A-(M), (M) (M)(A)
Flag
NVGBHIZC -------C -------C MM----Z-
---------------------0 --0-----0--0---------C -------C -------C -------C --------------C -------C ---------------------1 --1-----------N-----ZN-----Z-
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GMS800 Series
Branch / Jump Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mnemonic
BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BMI rel BNE rel BPL rel BRA rel BVC rel BVS rel CALL !abs CALL [dp] CBNE dp,rel CBNE dp+X,rel DBNE dp,rel DBNE Y,rel JMP !abs JMP [!abs] JMP [dp] PCALL upage
Op Code
y2 y3 x2 x3 50 D0 F0 90 70 10 2F 30 B0 3B 5F FD 8D AC 7B 1B 1F 3F 4F
Byte No
2 3 2 3 2 2 2 2 2 2 2 2 2 3 2 3 3 3 2 3 3 2 2
Cycle No
4/6 5/7 4/6 5/7 2/4 2/4 2/4 2/4 2/4 2/4 4 2/4 2/4 8 8 5/7 6/8 5/7 4/6 3 5 4 6 Branch if bit clear :
Operation
if ( bit ) = 0 , then pc ( pc ) + rel Branch if bit set : if ( bit ) = 1 , then pc ( pc ) + rel Branch if carry bit clear if ( C ) = 0 , then pc ( pc ) + rel Branch if carry bit set if ( C ) = 1 , then pc ( pc ) + rel Branch if equal if ( Z ) = 1 , then pc ( pc ) + rel Branch if minus if ( N ) = 1 , then pc ( pc ) + rel Branch if not equal if ( Z ) = 0 , then pc ( pc ) + rel Branch if minus if ( N ) = 0 , then pc ( pc ) + rel Branch always pc ( pc ) + rel Branch if overflow bit clear if (V) = 0 , then pc ( pc) + rel Branch if overflow bit set if (V) = 1 , then pc ( pc ) + rel Subroutine call M( sp)( pcH ), spsp - 1, M(sp) (pcL), sp sp - 1, if !abs, pc abs ; if [dp], pcL ( dp ), pcH ( dp+1 ) . Compare and branch if not equal : if ( A ) ( M ) , then pc ( pc ) + rel. Decrement and branch if not equal : if ( M ) 0 , then pc ( pc ) + rel. Unconditional jump pc jump address U-page call M(sp) ( pcH ), sp sp - 1, M(sp) ( pcL ), sp sp - 1, pcL ( upage ), pcH "0FFH" . Table call : (sp) ( pcH ), sp sp - 1, M(sp) ( pcL ),sp sp - 1, pcL (Table vector L), pcH (Table vector H)
Flag
NVGBHIZC ---------------
----------------------------------------------------------------
----------------------
--------
--------
24
TCALL n
nA
1
8
--------
MAR. 2005
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GMS800 Series
Control Operation & Etc.
No.
1 2 3 4 5 6 7 8 9 10 11 12 13
Mnemonic
BRK DI EI NOP POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET
Op Code
0F 60 E0 FF 0D 2D 4D 6D 0E 2E 4E 6E 6F
Byte No
1 1 1 1 1 1 1 1 1 1 1 1 1
Cycle No
8 3 3 2 4 4 4 4 4 4 4 4 5
Operation
Software interrupt : B "1", M(sp) (pcH), sp sp-1, M(s) (pcL), sp sp - 1, M(sp) (PSW), sp sp -1, pcL ( 0FFDEH ) , pcH ( 0FFDFH) . Disable all interrupts : I "0" Enable all interrupt : I "1" No operation sp sp + 1, A M( sp ) sp sp + 1, X M( sp ) sp sp + 1, Y M( sp ) sp sp + 1, PSW M( sp ) M( sp ) A , sp sp - 1 M( sp ) X , sp sp - 1 M( sp ) Y , sp sp - 1 M( sp ) PSW , sp sp - 1 Return from subroutine sp sp +1, pcL M( sp ), sp sp +1, pcH M( sp ) Return from interrupt sp sp +1, PSW M( sp ), sp sp + 1, pcL M( sp ), sp sp + 1, pcH M( sp ) Stop mode ( halt CPU, stop oscillator )
Flag
NVGBHIZC ---1-0------0------1---------------restored --------
--------
14 15
RETI STOP
7F EF
1 1
6 3
restored --------
viii
MAR. 2005
B. MASK ORDER SHEET
Mask Order & Verification Sheet MC80C02
Customer should write inside thick line box.
- MC
2. Device Information
Package File Name 44MQFP ( 8K 16K )
Set "00H" in blanked area
* PFD Option
1. Customer Information
Company Name Application Order Date Tel: E-mail address: Name & Signature:
YYYY MM DD
42SDIP ) .OTP 24K
ROM Size (bytes) Mask Data Check Sum (
Fax:
3.0V 2.7V 2.4V Not use
(24K) A000 H (16K) C000 H (8K) E000 H .OTP file FFFFH
3. Marking Specification
(Please check mark into
08 or 16 or 24
)
Customer's logo
MC80C02XX-MC MC80C02XX-MC YYWW KOREA YYWW KOREA
Customer logo is not required.
If the customer logo must be used in the special mark, please submit a clean original of the logo. Customer's part number
4. Delivery Schedule
Date Customer sample Risk order
YYYY MM DD
Quantity pcs pcs
MagnaChip Confirmation
YYYY
MM
DD
5. ROM Code Verification
Please confirm out verification data.
YYYY
Verification date: Check sum: Tel: E-mail address: Name & Signature: Fax:
MM
DD
YYYY
Approval date:
MM
DD
I agree with your verification data and confirm you to make mask set. Tel: E-mail address: Name & Signature: Fax:

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